mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 250

• Manufacturer Part Number: mc68ec060
• Description: Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
• Manufacturer: Freescale Semiconductor, Inc

Exception Processing
this example, the instruction has two faults (instruction access error and operand access
error), but the faults are not simultaneous and appear as an operand access error on the
source address and an instruction access error on the destination address to the processor.
Another item to note is that for instructions with indirect addresses, the processing of the
indirection is always completed prior to the instruction entering normal OEP sequence con-
trol.
To illustrate the handling of multiple exceptions, consider first a pending interrupt being
posted while a program is executing in trace mode (i.e., bit 15 of the SR is set).
Since the processor always samples for pending interrupts and traces at the conclusion of
instruction execution, both the trace and the interrupt appear simultaneous to the processor.
Since the trace has higher priority than the interrupt (4.0 versus 4.1), trace exception pro-
cessing begins. After the first instruction of the trace exception handler has been executed,
the processor again samples for pending interrupts. Providing the previous interrupt is still
pending, the processor now begins interrupt exception processing. As the interrupt handler
completes execution, control returns to the trace handler. As the trace handler completes,
control returns to the original program.
As a second example of the handling of multiple exceptions, consider the prior scenario (a
pending interrupt being posted while a program is executing in trace mode) at the same time
a TRAP instruction enters the OEP.
As described before, since the processor always samples for pending interrupts and traces
at the conclusion of instruction execution, both the trace and the interrupt appear simulta-
neous to the processor. Since the trace has higher priority than the interrupt, trace exception
processing begins. After the first instruction of the trace exception handler has been exe-
cuted, the processor again samples for pending interrupts. Providing the previous interrupt
is still pending, the processor begins interrupt exception processing. As the interrupt handler
completes execution, control returns to the trace handler. As the trace handler completes,
control returns to the original program, where the TRAP instruction is executed, causing that
exception to occur.
Note that if the processor is executing in trace mode when a group 2 or 3 exception is sig-
naled, a trace exception will not be generated. This means that for the second example, as
the TRAP exception handler completes its execution and performs its RTE, the next instruc-
tion of the program sequence will be executed before the next trace exception is performed
(the MC68060 will not trace immediately after the TRAP). If tracing is required immediately
following a group 2 or 3 exception, the SR contained in the exception stack frame should be
checked before returning to the next instruction. If the stacked SR indicates that the proces-
sor was executing in trace mode, the trace handler should be executed to account for the
instruction that initiated the exception.
Considering the previous example, the TRAP handler should check the stacked SR, and
since the processor was executing in trace mode, pass control to the trace handler. If this
check is not made, the next trace exception will not occur until the instruction after the TRAP
has completed execution.
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M68060 USER’S MANUAL
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