mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 327

• Manufacturer Part Number: mc68ec060
• Description: Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
• Manufacturer: Freescale Semiconductor, Inc

Applications Information
gal instruction exception is taken. This instruction must be removed from existing MC68040
software since it is not emulated in the M68060SP.
The MC68060 compensates for the lack of these instructions by providing extensive infor-
mation in the FSLW in the access error stack frame. In addition, a new instruction, PLPA, is
added to translate a logical to physical address by initiating a table search. This instruction
may be used to provide most of the function of the PTEST instruction. As with the PTEST
instruction, PLPA loads the valid page descriptor into the ATC when the table search it ini-
tiates executes successfully.
If it is absolutely necessary to emulate the PTEST and the MOVEC of the MMUSR, Motorola
provides assembly source code for these instructions in the bulletin board (see C.5.4
AESOP Electronic Bulletin Board for bulletin board details). The source code is provided
as-is and is only a rough approximation of these instructions and may need customizing. No
documentation is provided other than what is available in the source code.
11.1.2.3 CONTEXT SWITCH INTERRUPT HANDLERS. Context switch interrupt handlers
that use the same virtual address to map into multiple physical address locations must flush
the branch cache via the MOVEC to CACR instruction. The reason for this is that the branch
cache is a logical cache and not a physical cache. For systems that transparently translate
logical addresses to physical addresses, the branch cache need not be flushed.
In multiprocessor systems, care must be taken so that saved contexts generated by an
MC68040-based node not be restored into an MC68060-based node, or vice-versa. The
floating-point frames are different between an MC68040 and MC68060; incorrect swapping
of contexts may cause format errors to be incurred.
If the context switch interrupt handler uses a nonmaskable interrupt (level 7), CAS (mis-
aligned operands) or CAS2 instruction emulation may result in data corruption. There is no
good workaround except by either avoid using the level 7 interrupt for context switching, or
by using external hardware to block the interrupt lines from reporting an interrupt whenever
LOCK is asserted.
11.1.2.4 TRACE HANDLERS. The MC68060 does not implement “trace on change of flow”.
Debug software that rely on this feature must take this into consideration. When a change
of flow trace encoding is encountered, the processor does not trace.
11.1.2.5 I/O DEVICE DRIVER SOFTWARE. The MC68060, like the MC68040, has a
restart model, and device drivers that have been written for the MC68040 probably do not
need any modification in device driver software when porting to the MC68060; however
there are a few issues to consider.
The cache mode (CM) encoding on the TTRs and the page descriptors is different between
the MC68060 and MC68040. The MC68060 executes reads and writes in strict program
order, and therefore, whenever the CM bits indicate either a noncachable precise or non-
cachable imprecise, the accesses are serialized. Areas that are marked cache-inhibited
serialized for I/O devices should not be affected adversely by the cache mode change. Oth-
erwise, the TTR format and the page descriptor formats have not changed for the MC68060.
MOTOROLA
M68060 USER’S MANUAL
11-5