mc68ec060 Freescale Semiconductor, Inc, mc68ec060 Datasheet - Page 230

no-image

mc68ec060

Manufacturer Part Number
mc68ec060
Description
Mc68060 Superscalar 68k Microprocessor Including The Lc060 And Ec060
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc68ec060RC50
Manufacturer:
NXP
Quantity:
1 746
Part Number:
mc68ec060ZU50
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68ec060ZU66
Manufacturer:
MOTOROLA
Quantity:
256
Part Number:
mc68ec060ZU66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68ec060ZU66
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
mc68ec060ZU75
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
loaded into the internal counter and the counter decrements every rising BCLK edge. As
long as the counter has a non-zero count value, the MC68060 ignores the acknowledge ter-
mination signals. Once the counter reaches zero, the MC68060 asserts SAS for one BCLK
period and begins to sample the acknowledge termination signals and acts accordingly. This
process repeats for the rest of the line transfer cycle.
To aid in system debug for system designs that continuously assert TA, a status signal,
SAS, is provided to indicate which rising BCLK edge the MC68060 begins to sample
acknowledge termination signals. SAS is negated on the next rising BCLK edge if the bus
cycle ends or if the next ignore state count value is non-zero. Aside from being a status sig-
nal, SAS may be used in conjunction with some decode address bits to generate the CLA
signal or TA signal shown in Figure 7-24.
Figure 7-51 shows an example of how the MC68060 behaves when the acknowledge termi-
nation ignore state mode is enabled. In this example, the read primary ignore state count
value and the read secondary ignore state count value are initialized to a value of one during
reset. On the first long-word access, TA is asserted immediately, but data is not registered
until the rising edge of C4. On the next long-word access, the secondary count value takes
effect. In a similar manner, TA is ignored until the rising edge of C6. On the last long-word
access of the line, the secondary ignore state count expires before TA is asserted. There-
fore, more wait states are added until TA is asserted and recognized on the rising edge of
C12.
MOTOROLA
ADDRESS AND
ATTRIBUTES
D31–D0
BCLK
SAS
R/W
TS
TA
Figure 7-51. Acknowledge Termination Ignore State Example
C1
READ PRIMARY IGNORE STATE COUNT = 1
READ SECONDARY IGNORE STATE COUNT = 1
C2
IGNORED
C3
C4
M68060 USER’S MANUAL
IGNORED
C5
C6
IGNORED
C7
C8
IGNORED
C9
C10
Bus Operation
C11
C12
7-75

Related parts for mc68ec060