dp83902a National Semiconductor Corporation, dp83902a Datasheet - Page 11

• Manufacturer Part Number: dp83902a
• Description: St-nictm Serial Network Interface Controller For Twisted Pair
• Manufacturer: National Semiconductor Corporation

4 0 Functional Description
In order to prevent distortion on the transmitted frequency
the total capacitance seen by the crystal should equal the
total load capacitance On a standard parallel set-up as
shown in the diagram below the 2 load caps C1 and C2
should equal 2C1 the spec load cap (due to the capacitors
acting in series) less any stray capacitances
Thus the trim capacitors required can be calculated as fol-
lows
C1
C2
The value of STNIC pins X1 and X2 is in the region of 5 pF
NIC (Media Access Control) MODULE
RECEIVE DESERIALIZER
The Receive Deserializer is activated when the input signal
Carrier Sense is asserted to allow incoming bits to be shift-
ed into the shift register by the receive clock The serial
receive data is also routed to the CRC generator checker
The Receive Deserializer includes a synch detector which
detects the SFD (Start of Frame Delimiter) to establish
where byte boundaries within the serial bit stream are locat-
ed After every eight receive clocks the byte wide data is
transferred to the 16-byte FIFO and the Receive Byte Count
is incremented The first six bytes after the SFD are
checked for valid comparison by the Address Recognition
Logic If the Address Recognition Logic does not recognize
the packet the FIFO is cleared
CRC GENERATOR CHECKER
During transmission the CRC logic generates a local CRC
field for the transmitted bit sequence The CRC encodes all
fields after the SFD The CRC is shifted out MSB first follow-
ing the last transmit byte During reception the CRC logic
generates a CRC field from the incoming packet This local
CRC is serially compared to the incoming CRC appended to
the end of the packet by the transmitting node If the local
and received CRC match a specific pattern will be generat-
ed and decoded to indicate no data errors Transmission
errors result in different pattern and are detected resulting
in rejection of a packet (if so programmed)
TRANSMIT SERIALIZER
The Transmit Serializer reads parallel data from the FIFO
and serializes it for transmission The serializer is clocked by
the transmit clock generated internally The serial data is
also shifted into the CRC generator checker At the begin-
ning of each transmission the Preamble and Synch Gener-
ator append 62 bits of 1 0 preamble and a 1 1 synch pat-
tern After the last data byte of the packet has been serial-
ized the 32-bit FCS field is shifted directly out of the CRC
generator In the event of a collision the Preamble and
Synch generators are used to generate a 32-bit JAM pattern
of all 1’s
and Cd1
and Cd2
e
e
2XC1
2XC1
b
b
e
e
(Cb1
(Cb2
X1 dev cap
X2 dev cap
a
a
Cd1) Where Cb1
Cd2) Where Cb2
e
e
Board cap on X1
Board cap on X2
TL F 11157 – 52
(Continued)
11
ADDRESS RECOGNITION LOGIC
The address recognition logic compares the Destination Ad-
dress Field (first 6 bytes of the received packet) to the Phys-
ical address registers stored in the Address Register Array
If any one of the six bytes does not match the pre-pro-
grammed physical address the Protocol Control Logic re-
jects the packet All multicast destination addresses are fil-
tered using a hashing technique (See register description )
If the multicast address indexes a bit that has been set in
the filter bit array of the Multicast Address Register Array
the packet is accepted otherwise it is rejected by the Proto-
col Control Logic Each destination address is also checked
for all 1’s which is the reserved broadcast address
FIFO AND BUS OPERATIONS
Overview
To accommodate the different rates at which data comes
from (or goes to) the network and goes to (or comes from)
the system memory the ST-NIC contains a 16-byte FIFO for
buffering data between the media The FIFO threshold is
programmable When the FIFO has filled to its programmed
threshold the local DMA channel transfers these bytes (or
words) into local memory It is crucial that the local DMA is
given access to the bus within a minimum bus latency time
otherwise a FIFO underrun (or overrun) occurs
FIFO underruns or overruns are caused by two conditions
(1) the bus latency is so long that the FIFO has filled (or
emptied) from the network before the local DMA has serv-
iced the FIFO and (2) the bus latency has slowed the
throughput of the local DMA to a point where it is slower
than the network data rate (10 Mbit sec) This second con-
dition is also dependent upon DMA clock and word width
(byte wide or word wide) The worst case condition ultimate-
ly limits the overall bus latency which the ST-NIC can toler-
ate
Beginning of Receive
At the beginning of reception the ST-NIC stores the entire
Address field of each incoming packet in the FIFO to deter-
mine whether the address matches the ST-NIC’s Physical
Address Registers or maps to one of its Multicast Registers
This causes the FIFO to accumulate 8 bytes Furthermore
there are some synchronization delays in the DMA PLA
Thus the actual time to when BREQ is asserted from the
time the Start of Frame Delimiter (SFD) is detected is
7 8 ms This operation affects the bus latencies at 2- and
4-byte thresholds during the first receive BREQ since the
FIFO must be filled to 8 bytes (or 4 words) before issuing a
BREQ
End of Receive
When the end of a packet is detected by the ENDEC mod-
ule the ST-NIC enters its end of packet processing se-
quence emptying its FIFO and writing the status information
at the beginning of the packet The ST-NIC holds onto the
bus for the entire sequence The longest time BREQ may be
extended occurs when a packet ends just as the ST-NIC
performs its last FIFO burst The ST-NIC in this case per-
forms a programmed burst transfer followed by flushing the
remaining bytes in the FIFO and completes by writing the
header information to memory The following steps occur
during this sequence
1 ST-NIC issues BREQ because the FIFO threshold has
2 During the burst packet ends resulting in BREQ extend-
been reached
ed