dp83902a National Semiconductor Corporation, dp83902a Datasheet - Page 41

• Manufacturer Part Number: dp83902a
• Description: St-nictm Serial Network Interface Controller For Twisted Pair
• Manufacturer: National Semiconductor Corporation

13 0 Bus Arbitration and Timing
The ST-NIC operates in three possible modes
Upon power-up the ST-NIC is in an indeterminate state Af-
ter receiving a hardware reset the ST-NIC is a bus slave in
the Reset State the receiver and transmitter are both dis-
abled in this state The reset state can be re-entered under
three conditions soft reset (Stop Command) hard reset
(RESET input) or an error that shuts down the receiver of
transmitter (FIFO underflow or overflow) After initialization
of registers the ST-NIC is issued a Start command and the
ST-NIC enters Idle state Until the DMA is required the
ST-NIC remains in idle state The idle state is exited by a
request from the FIFO on the case of receiver or transmit or
from the Remote DMA in the case of Remote DMA



BUS MASTER (WHILE PERFORMING DMA)
BUS SLAVE (WHILE BEING ACCESSED BY CPU)
IDLE
16-Bit Address 8-Bit Data
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operation After acquiring the bus in a BREQ BACK hand-
shake the Remote or Local DMA transfer is completed and
the ST-NIC re-enters the idle state
DMA TRANSFERS TIMING
The DMA can be programmed for the following types of
transfers
All DMA transfers use BSCK for timing 16-Bit Address
modes require 4 BSCK cycles as shown below
16-Bit Address 8-bit Data Transfer
16-Bit Address 16-bit Data Transfer
32-Bit Address 8-bit Data Transfer
32-Bit Address 16-bit Data Transfer
TL F 11157 – 21
TL F 11157 – 22