dp83902a National Semiconductor Corporation, dp83902a Datasheet - Page 32

• Manufacturer Part Number: dp83902a
• Description: St-nictm Serial Network Interface Controller For Twisted Pair
• Manufacturer: National Semiconductor Corporation

10 0 Internal Registers
10 3 REGISTER DESCRIPTIONS (Continued)
RECEIVE CONFIGURATION REGISTER (RCR)
This register determines operation of the ST-NIC during reception of a packet and is used to program what types of packets to
accept
Note D2 and D3 are ‘‘OR’d’’ together i e if D2 and D3 are set the ST-NIC will accept broadcast and multicast addresses as well as its own physical address To
establish full promiscuous mode bits D2 D3 and D4 should be set In addition the multicast hashing array must be set to all 1’s in order to accept all multicast
addresses
Bit
D0
D1
D2
D3
D4
D5
D6
D7
SEP
AR
AB
AM
PRO
MON
Reserved
Reserved
Symbol
Save Errored Packets
0 Packets with receive errors are rejected
1 Packets with receive errors are accepted Receive errors are CRC and Frame Alignment
errors
Accept Runt Packets This bit allows the receiver to accept packets that are smaller than 64
bytes The packet must be at least 8 bytes long to be accepted as a runt
0 Packets with fewer than 64 bytes rejected
1 Packets with fewer than 64 bytes accepted
Accept Broadcast Enables the receiver to accept a packet with an all 1’s destination address
0 Packets with broadcast destination address rejected
1 Packets with broadcast destination address accepted
Accept Multicast Enables the receiver to accept a packet with a multicast address All multicast
addresses must pass the hashing array
0 Packets with multicast destination address not checked
1 Packets with multicast destination address checked
Promiscuous Physical Enables the receiver to accept all packets with a physical address
0 Physical address of node must match the station address programmed in PAR0 – PAR5
1 All packets with physical addresses accepted
Monitor Mode Enables the receiver to check addresses and CRC on incoming packets without
buffering to memory The Missed Packet Tally counter will be incremented for each recognized
packet
0 Packets buffered to memory
1 Packets checked for address match good CRC and Frame Alignment but not buffered to
memory
Reserved
Reserved
7
(Continued)
6
MON
5
0CH (WRITE)
PRO
4
32
AM
3
Description
AB
2
AR
1
SEP
0