dp83902a National Semiconductor Corporation, dp83902a Datasheet - Page 60

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dp83902a

Manufacturer Part Number
dp83902a
Description
St-nictm Serial Network Interface Controller For Twisted Pair
Manufacturer
National Semiconductor Corporation
Datasheet

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15 0 Switching Characteristics
Note 1 The addition of wait states affects the count of deserialized bytes and is limited to a number of bus clock cycles depending on the bus clock and network
rates The allowable wait states are found in the table below (Assumes 10 Mbit sec data rate )
Table assumes 10 MHz network clock
BSCK (MHz)
Symbol
ews
ewr
10
12
14
16
18
20
8
Byte Transfer
External Wait Setup to T3 0Clock (Note 1)
External Wait Release Time (Note 1)
Max
0
0
1
1
1
2
2
of Wait States
Parameter
Word Transfer
1
1
2
2
3
3
4
AC Specs DP83902A Note All Timing is Preliminary (Continued)
Wait State Insertion
60
The number of allowable wait states in byte mode can be
calculated using
tnw
tbsck
The number of allowable wait states in word mode can be
calculated using
W
W
W
(byte mode)
(word mode)
Min
10
15
e
e
e
e
e
Number of Wait States
Network Clock Period
BSCK Period


4 5 tbsck
2 tbsck
5 tnw
8 tnw
b
b
1
Max
1
J
J
TL F 11157 – 41
Units
ns
ns

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