dp83902a National Semiconductor Corporation, dp83902a Datasheet - Page 39

• Manufacturer Part Number: dp83902a
• Description: St-nictm Serial Network Interface Controller For Twisted Pair
• Manufacturer: National Semiconductor Corporation

12 0 Loopback Diagnostics
3 Verify that the Address Recognition Logic can
LOOPBACK OPERATION IN THE ST-NIC
Loopback is a modified form of transmission using only half
of the FIFO This places certain restrictions on the use of
loopback testing When loopback mode is selected in the
TCR the FIFO is split A packet should be assembled in
memory with programming of TPSR and TBCR0 TBCR1
registers When the transmit command is issued the follow-
ing operations occur
Transmitter Actions
1 Data is transferred from memory by the DMA until the
2 The ST-NIC generates 56 bits of preamble followed by an
3 Data transferred from FIFO to serializer
4 If CRC
5 At end of Transmission PTX bit set in ISR
Receiver Actions
1 Wait for synch all preamble stripped
2 Store packet in FIFO increment receive byte count for
3 If CRC
4 At the end of receive the receive byte count is written
EXAMPLES
The following examples show what results can be expected
from a properly operating ST-NIC during loopback The re-
strictions and results of each type of loopback are listed for
reference The loopback tests are divided into two sets of
tests One to verify the data path CRC generation and byte
count through all three paths The second set of tests uses
internal loopback to verify the receiver’s CRC checking and
address recognition For all of the tests the DCR was pro-
grammed to 40H
Note 1 Since carrier sense and collision detect are generated in the EN-
Note 2 CRC errors are always indicated by the receiver if CRC is appended
Note 3 Only the PTX bit in the ISR is set the PRX bit is only set if status is
Note 4 All values are hex
ST-NIC Internal
a) Recognize address match packets
b) Reject packets that fail to match an address
FIFO is filled For each transfer TBCR0 and TBCR1 are
decremented (Subsequent burst transfers are initiated
when the number of bytes in the FIFO drops below the
programmed threshold )
8-bit synch pattern
and the last byte transmitted is the last byte from the
FIFO (Allows software CRC to be appended) If CRC
0 ST-NIC calculates and appends four bytes of CRC
each incoming byte
CRC errors If CRC
CRC errors CRC error bit always set in RSR (for address
matching packets)
into the FIFO and the receive status register is updated
The PRX bit is typically set in the RSR even if the address
does not match If CRC errors are forced the packet
must match the address filters in order for the CRC error
bit in the RSR to be set
Path
DEC module they are blocked during NIC loopback Carrier and CD
heartbeat are not seen and the CRS and CDH bits are set
by the transmitter
written to memory In loopback this action does not occur and the
PRX bit remains 0 for all loopback modes
e
e
1 in TCR the CRC is not calculated by ST-NIC
1 in TCR receiver checks incoming packet for
TCR RCR
02
e
0 in TCR receiver does not check
1F
(Note 1) (Note 2) (Note 3)
TSR
53
RSR
02
(Continued)
ISR
02
e
39
Note 1 CDH is set CRS is not set since it is generated by the external
Note 1 CDH and CRS should not be set The TSR however could also
Note 2 The ISR will contain 08H if packet is not transmittable
Note 3 During external loopback the ST-NIC is now exposed to network
Note 4 All values are hex
CRC AND ADDRESS RECOGNITION
The next three tests exercise the address recognition logic
and CRC These tests should be performed using internal
loopback only so that the ST-NIC is isolated from interfer-
ence from the network These tests also require the capabil-
ity to generate CRC in software
The address recognition logic cannot be directly tested The
CRC and FAE bits in the RSR are only set if the address in
the packet matches the address filters If errors are expect-
ed to be set and they are not set the packet has been
rejected on the basis of an address mismatch The following
sequence of packets will test the address recognition logic
The DCR should be set to 40H and the TCR should be set
to 03H with a software generated CRC
Note 1 Status will read 21H if multicast address used
Note 2 Status will read 22H if multicast address used
Note 3 In test A the RSR is set up In test B the address is found to match
Note 4 All values are hex
NETWORK MANAGEMENT FUNCTIONS
Network management capabilities are required for mainte-
nance and planning of a local area network The ST-NIC
supports the minimum requirement for network manage-
ment in hardware the remaining requirements can be met
with software counts There are three events that software
alone can not track during reception of packets CRC errors
Frame Alignment errors and missed packets
ST-NIC External
ST-NIC Internal
Test A
Test B
Test C
Test
Path
Path
encoder decoder
contain 01H 03H 07H and a variety of other values depending on
whether collisions were encountered or the packet was deferred
traffic It is therefore possible for the contents of both the Receive
portion of the FIFO and the RSR to be corrupted by any other
packet on the network Thus in a live network the contents of the
FIFO and RSR should not be depended on The ST-NIC will still
abide by the standard CSMA CD protocol in external loopback
mode (i e The network will not be disturbed by the loopback pack-
et )
since the CRC is flagged as bad Test C proves that the address
recognition logic can distinguish a bad address and does not notify
the RSR of the bad CRC The receiving CRC is proven to work in
test A and test B
Packet Contents
Non-Matching
Address
Matching
Matching
TCR RCR
TCR
06
04
1F
RCR
1F
(Note 1)
Good
CRC
TSR
Bad
Bad
(Note 1)
03
TSR
43
RSR
02
01 (Note 1)
02 (Note 2)
RSR
Results
02
RSR
01
(Note 2)
ISR
02
ISR
02