dp83902a National Semiconductor Corporation, dp83902a Datasheet - Page 6

• Manufacturer Part Number: dp83902a
• Description: St-nictm Serial Network Interface Controller For Twisted Pair
• Manufacturer: National Semiconductor Corporation

BUS INTERFACE PINS (Continued)
NETWORK INTERFACE PINS
Pin No
55 56
58 59
64 65
PQFP
2 0 Pin Description
43
45
52
47
49
50
51
69
73
70
71
72
74
Pin No
54 55
PLCC
56 57
61 62
45
46
53
48
50
51
52
67
68
69
70
71
Pin No
54 55
AVJG
56 57
61 62
40
42
50
45
47
48
49
65
70
66
67
69
71
BACK
BREQ
RESET
POL
TXE TX
COL
TEST
TXOd
TXO
TXO
TXOd
RXI
RXI
GDLNK
LNKDIS
SQSEL
20 MHz
X1
GND
X2
SEL
Name
(Continued)
Pin
a
b
a
b
b
a
I O
I O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
BUS ACKNOWLEDGE Bus Acknowledge is an active high signal indicating that
the CPU has granted the bus to the DP83902A If immediate bus access is
desired BREQ should be tied to BACK Tying BACK to V
deadlock
BUS REQUEST Bus Request is an active high signal used to request the bus for
DMA transfers This signal is automatically generated when the FIFO needs
servicing
RESET Reset is active low and places the DP83902A in a reset mode
immediately No packets are transmitted or received by the DP83902A until STA
bit is set Affects Command Register Interrupt Mask Register Data Configuration
Register and Transmit Configuration Register The DP83902A will execute reset
within 10 BSCK cycles
POLARITY A TTL MOS active high output This signal is normally in the low
state When the TPI module detects seven consecutive link pulses or three
consecutive received packets with reversed polarity POL is asserted
TRANSMIT ENABLE TRANSMIT A TTL MOS active high output It is asserted
for approximately 50 ms whenever the DP83902A transmits data in either AUI or
TPI modes
COLLISION A TTL MOS active high output It is asserted for approximately 50
ms whenever the DP83902A detects a collision in either the AUI or TPI modes
FACTORY TEST INPUT Used to check the chip’s internal functions This should
be tied low during normal operation
TWISTED PAIR TRANSMIT OUTPUTS These high drive CMOS level outputs
are resistively combined external to the chip to produce a differential output
signal with equalization to compensate for Intersymbol Interference (ISI) on the
twisted pair medium
TWISTED PAIR RECEIVE INPUTS These inputs feed a differential amplifier
which passes valid data to the ENDEC module
GOOD LINK LINK DISABLE This pin has a dual function both input and output
The function is latched by the DP83902A on the rising edge of the Reset signal
i e on the chip returning to normal operation after reset
As an output this pin is configured as an open drain N-channel device and is
suitable for driving a LED It will be latched as output on removal of chip reset if
connected to a LED or left open circuit Under normal conditions (the twisted pair
link is not broken) the output will be low and the LED will be lit The open drain
output will be switched off if the twisted pair link has been detected to be broken
It is recommended that the color of the LED be green This output will be pulled
high in AUI mode by an internal resistor of approximately 15 kX
When this pin which has an internal pull-up resistor to V
an input and the link integrity checking is disabled
TPI SQUELCH SELECT This pin selects the TPI module input squelch
thresholds When tied low the input squelch threshold on the RXI
complies to 10BASE-T specification When set high the RXI
with reduced squelch levels allowing its use with longer lengths of cable or cable
with higher losses If this pin is left unconnected an internal pulldown causes the
ST-NIC’s TPI to default to the higher squelch level
20 MHz This is a TTL MOS level signal It is a buffered version of the oscillator
X2 It is suitable to drive external logic
EXTERNAL OSCILLATOR INPUT
GROUND X2 If an oscillator is used this pin should be tied to ground and if a
crystal is used this pin should be tied directly to the crystal
MODE SELECT When high TX
state When low Transmit
state at the transformer’s primary
6
a
is positive with respect to Transmit
a
Description
and TX
b
are the same voltage in the idle
DD
CC
is tied low it becomes
g
will result in a
input operates
b
g
in the idle
inputs