dp83902a National Semiconductor Corporation, dp83902a Datasheet - Page 45

• Manufacturer Part Number: dp83902a
• Description: St-nictm Serial Network Interface Controller For Twisted Pair
• Manufacturer: National Semiconductor Corporation

13 0 Bus Arbitration and Timing
The FIFO at the Beginning of Transmit
Before transmitting the ST-NIC performs a prefetch from
memory to load the FIFO The number of bytes prefetched
Maximum Bus Latency for Byte Mode
TL F 11157 – 60
Transmit Prefetch Timing
(Continued)
45
is the programmed FIFO threshold The next BREQ is not
issued until after the ST-NIC actually begins transmitting
data i e after SFD The Transmit Prefetch diagram illus-
trates this process
Maximum Bus Latency for Word Mode
TL F 11157 – 59
TL F 11157 – 61