dp83902a National Semiconductor Corporation, dp83902a Datasheet - Page 5

• Manufacturer Part Number: dp83902a
• Description: St-nictm Serial Network Interface Controller For Twisted Pair
• Manufacturer: National Semiconductor Corporation

BUS INTERFACE PINS (Continued)
14 15 17
18 22 23
Pin No
2 0 Pin Description
10 – 12
PQFP
25 26
4 – 8
27
28
29
30
31
32
33
36
37
39
41
42
Pin No
12 – 23
28 – 31
PLCC
32
33
34
35
36
37
38
40
41
42
43
44
7 9 – 15
Pin No
2 – 4 6
20 – 23
AVJG
25
26
27
28
29
30
31
34
35
36
37
39
(Continued)
AD0 –
AD15
ADS0
CS
MWR
MRD
SWR
SRD
ACK
BSCK
RACK
PWR
READY
PRQ
ADS1
Name
Pin
I O Z
I O Z
O Z
O Z
O Z
I O
O
O
I
I
I
I
I
I
MULTIPLEXED ADDRESS DATA BUS
ADDRESS STROBE 0
CHIP SELECT Chip Select places controller in slave mode for mP access to
internal registers Must be valid through data portion of bus cycle RA0 – RA3
are used to select the internal register SWR and SRD select direction of
data transfer
MASTER WRITE STROBE (Strobe for DMA transfers)
Active low during write cycles (t2 t3 tw) to buffer memory Rising edge
coincides with the presence of valid output data TRI-STATE until BACK
asserted
MASTER READ STROBE (Strobe for DMA transfers)
Active during read cycles (t2 t3 tw) to buffer memory Input data must be
valid on rising edge of MRD TRI-STATE until BACK asserted
SLAVE WRITE STROBE Strobe from CPU to write an internal register
selected by RA0 – RA3 Data is latched into the DP83902A on the rising
edge of this input
SLAVE READ STROBE Strobe from CPU to read an internal register
selected by RA0 – RA3 The register data is output when SRD goes low
ACKNOWLEDGE Active low when DP83902A grants access to CPU Used
to insert WAIT states to CPU until DP83902A is synchronized for a register
read or write operation
BUS CLOCK This clock is used to establish the period of the DMA memory
cycle Four clock cycles (t1 t2 t3 t4) are used per DMA cycle DMA
transfers can be extended by one BSCK increment using the READY input
READ ACKNOWLEDGE Indicates that the system DMA or host CPU has
read the data placed in the external latch by the DP83902A The DP83902A
will begin a read cycle to update the latch
PORT WRITE Strobe used to latch data from the DP83902A into external
latch for transfer to host memory during Remote Read transfers The rising
edge of PWR coincides with the presence of valid data on the local bus
READY This pin is set high to insert wait states during a DMA transfer The
DP83902A will sample this signal at t3 during DMA transfers
PORT REQUEST ADDRESS STROBE 1
Note This line will power up as TRI-STATE until the Data Configuration Register is programmed






During t1 of memory cycle AD0 – AD15 contain address
During t2 t3 t4 AD0 – AD15 contain data (word transfer mode)
During t2 t3 t4 AD0–AD7 contain data AD8–AD15 contain address (byte
transfer mode)
Direction of transfer is indicated by DP83902A on MWR MRD lines
Register Access with DMA inactive CS low and ACK returned from
DP83902A pins AD0–AD7 are used to read and write register data AD8–
AD15 float during I O transfers SRD SWR pins are used to select
direction of transfer
Bus Master with BACK input asserted
Input with DMA inactive and CS low latches RA0–RA3 inputs on falling
edge If high data present on RA0–RA3 will flow through latch
Output When Bus Master latches address bits (AD0–AD15) to external
memory during DMA transfers
32-BIT MODE If LAS is set in the Data Configuration Register this line is
programmed as ADS1 It is used to strobe addresses A16 – A31 into
external latches (A16 – A31 are the fixed addresses stored in RSAR0
RSAR1) ADS1 will remain at TRI-STATE until BACK is received
16-BIT MODE If LAS is not set in the Data Configuration Register this
line is programmed as PRQ and is used for Remote DMA Transfers The
DP83902A initiates a single remote DMA read or write operation by
asserting this pin In this mode PRQ will be a standard logic output
5
Description