peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 107

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

PEB 20534
PEF 20534
Multi Function Port (MFP)
6.1.2
LBI Bus Arbitration
In high performance systems it may be efficient to share external resources like memory
banks or peripheral devices among more than one bus controller. The LBI’s EBC block
supports this approach with the possibility to arbitrate the access to its external bus, i.e.
to the external devices.
This bus arbitration allows an external master to request the EBC’s bus via the LHOLD
input signal. The EBC acknowledges this request via the LHLDA output signal and will
float its bus signals in this case. The new master may now access the peripheral devices
or memory banks via the same interface lines as the EBC. During this time the DSCC4
can keep on executing internal processes, as long as it does not need access to the
external bus.
When the EBC needs access to its external bus while it is occupied by another bus
master, the bus is requested via the LBREQ output signal.
The external bus arbitration is enabled by setting bit ’HLDEN’ in the LBI Configuration
register LCONF to ‘1’. This bit is allowed to be cleared by software during the execution
of program sequences, where the external resources are required but cannot be shared
with other bus masters. In this case the EBC will not answer to LHOLD requests from
other external masters.
The pins LHOLD, LHLDA and LBREQ keep their function (bus arbitration) even after the
arbitration mechanism has been switched off by clearing bit ’HLDEN’.
All three pins are used for bus arbitration after bit ’HLDEN’ was set once.
Entering the Hold State:
Access to the EBC’s external bus is requested by driving its LHOLD input low. After
synchronizing this signal the EBC will complete a current external bus cycle (if any is
active), release the external bus and grant access to it by driving the LHLDA output low.
During hold state, the address bus, data bus and signals LALE, LRD, LWR, LBHE are
tri-stated.
Should the DSCC4 require access to its external bus during hold mode, it activates its
bus request output LBREQ to notify the arbitration circuitry. LBREQ is activated only
during hold mode. It will be inactive during normal operation.
Data Sheet
107
2000-05-30