peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 359

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
SSCPH
SSCHB
SSCBM
(3:0)
SSCBC
(3:0)
SSC Clock Phase Control
This bit selects the active clock phase for operation. The definition of the
leading clock edge depends on the setting of bit ’SSCPO’:
SSCPH=’0’
SSCPH=’1’
SSC Heading (Bit Order) Control
This bit selects if LSB or MSB is transmitted/received first:
SSCHB=’0’
SSCHB=’1’
SSC Data Width Control
Via this bit field, the data width (active part of the transmit and receive
buffers) can be selected in the range 2 to 16 bit:
SSCBM
’0000’
’0001’
’0010’
...
’1111’
SSC Shift Counter
This bit field is used by the SCC as shift counter and is updated with
every bit shift operation.
Transmit data is shifted with the leading clock edge,
receive data is latched with the trailing clock edge.
Transmit data is shifted with the trailing clock edge,
receive data is latched with the leading clock edge.
LSB first operation on transmit and receive.
MSB first operation on transmit and receive.
Data width:
Reserved. Do not use.
Data width is 2 bit.
Data width is 3 bit.
...
Data width is 16 bit.
359
Detailed Register Description
(configuration mode)
(configuration mode)
(configuration mode)
(operation mode)
PEB 20534
PEF 20534
2000-05-30