peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 208

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Table 31
Step
9
10
11
12
Data Sheet
Action by Host
Set appropriate channel configuration
bits (receive and transmit) and Action
Request (AR) bit in GCMDR.
Read
information
interrupts by writing a ’1’ back to the
bits, which indicate an interrupt
Enable the SCC receiver
(CCR2.RAC=’1’).
Activation of DMAC and SCC (cont’d)
GSTAR
and
for
acknowledge
interrupt
208
Action by DSCC4
After the DSCC4 has become bus
master the DMAC the internal DMA
channels for data transfer. When the
configuration was successful, the
DMAC sets GSTAR.ARACK=’1’.
If enabled, INT signal is activated and
the DMAC stores the corresponding
configuration interrupt vector in the
interrupt queue IQCFG located in the
shared memory. Moreover the DMAC
branches to the base receive/transmit
descriptor
BTDA) of the linked list.
In transmit direction it starts trans-
ferring data - if available - from shared
memory into the on chip central
transmit
receivers are not activated so far, no
data are received from SCCs.
SCC starts data reception. The
received data are transferred to the
central RFIFO. As soon as the
threshold of the RFIFO has been
reached, the DMAC transfers the data
into the shared memory.
Reset and Initialization Procedure
FIFO.
(referenced
Since
PEB 20534
PEF 20534
by
the
2000-05-30
BRDA/
SCCs