peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 380

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

HOLD:
HI:
NO:
Next
Receive
Descriptor
Pointer:
Receive
Data
Pointer:
Data Sheet
Hold (only valid when GMODE.CMODE=0)
It indicates whether the current descriptor is the last element of a linked list
or not:
Host Initiated Interrupt
If the HI bit is set, the corresponding DMAC generates an interrupt with set
HI bit after transferring all data bytes into the current data section.
Byte Number
This byte number defines the size of the receive data section allocated by
the host. It has to be a multiple of 4 bytes which is responsibility of the soft-
ware. The maximum buffer length is 8188 bytes (i.e. NO = 1FFC
HOLD=’0’: A next descriptor is available in the shared memory; after
HOLD=’1’: The current descriptor is the last one that is available for the
This 32-bit pointer contains the start address of the next receive descrip-
tor. After completion of the current receive descriptor the DSCC4 branches
to the next receive descriptor to continue reception. The receive descriptor
is read entirely at the beginning of reception and stored in on-chip mem-
ory. Therefore all information in the next descriptor must be valid when the
DSCC4 branches to this descriptor.
This pointer is not used if a receiver reset command is detected while the
DSCC4 still writes data to the current receive descriptor. In this case
BRDA is used as a pointer for the next receive descriptor to be branched
to.
This 32-bit pointer contains the start address of the receive data section.
The start address must be DWORD aligned.
checking the HOLD bit stored in the on-chip memory the
DMAC branches to next receive descriptor
DMAC. After completion of the current receive descriptor an
interrupt is generated and the corresponding DMAC channel
is deactivated for receive direction as long as the micropro-
cessor does not request an activation via the CMDR register.
380
Host Memory Organization
PEB 20534
PEF 20534
H
2000-05-30
).