peb20534 Infineon Technologies Corporation, peb20534 Datasheet - Page 297

• Manufacturer Part Number: peb20534
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
CHL(1..0)
RAC
DXS
XBRK
Character Length
This bit field selects the number of data bits within a character:
CHL = ’00’
CHL = ’01’
CHL = ’10’
CHL = ’11’
Receiver active
Switches the receiver between operational/inoperational states:
RAC=’0’
RAC=’1’
Disable Storage of XON/XOFF Characters
In ASYNC mode, XON/XOFF characters might be filtered out or stored
to the SCC receive FIFO:
DXS=’0’
DXS=’1’
Transmit Break
XBRK=’0’
XBRK=’1’
8-bit data.
7-bit data.
6-bit data.
5-bit data.
Receiver inactive, receive line is ignored.
Receiver active.
All received characters including XON/XOFF characters
are stored in the receive FIFO.
XON/XOFF characters are filtered out and not stored in
the receive FIFO.
Normal transmit operation.
Forces the TxD pin to ’low’ level immediately (break
condition), regardless of any character being currently
transmitted. This command is executed immediately with
the next rising edge of the transmit clock and further
transmission is disabled. The currently sent character is
lost.
Data stored in the SCC transmit FIFO will be sent as soon
as the break condition is cleared (XBRK=’0’). A transmit
reset command (bit ’XRES’ in register CMDR) does NOT
clear the break condition automatically.
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Detailed Register Description
(async/bisync modes)
(async mode)
(async mode)
PEB 20534
PEF 20534
(all modes)
2000-05-30