mt29f4g08aaa Micron Semiconductor Products, mt29f4g08aaa Datasheet - Page 16

• Manufacturer Part Number: mt29f4g08aaa
• Description: 4gb, 8gb, And 16gb X8 Nand Flash Memory
• Manufacturer: Micron Semiconductor Products

Data Input
READs
Ready/Busy#
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
Data is written to the data register on the rising edge of WE# when:
• CE#, CLE, and ALE are LOW, and
• the device is not busy
Data is input on I/O[7:0]. See Figure 55 on page 66 for additional data input details.
After a READ command is issued, data is transferred from the memory array to the data
register on the rising edge of WE#. R/B# goes LOW for
transfer is complete. When data is available in the data register, it is clocked out of the
part by RE# going LOW. See Figure 60 on page 68 for detailed timing information.
The READ STATUS (70h) command, TWO-PLANE/MULTIPLE-DIE READ STATUS (78h)
command, or the R/B# signal can be used to determine when the device is ready.
If a controller is using a timing of 30ns or longer for
proper timing. If
(EDO) timing.
The R/B# output provides a hardware method of indicating the completion of
PROGRAM, ERASE, and READ operations. The signal requires a pull-up resistor for
proper operation. The signal is typically HIGH, and transitions to LOW after the appro-
priate command is written to the device. The signal pin’s open-drain driver enables
multiple R/B# outputs to be OR-tied. The READ STATUS command can be used in place
of R/B#. Typically, R/B# is connected to an interrupt pin on the system controller (see
Figure 8 on page 17).
On the 8Gb MT29F8G08DAA, R/B# provides a status indication for the 4Gb section
enabled by CE#, and R/B2# does the same for the 4Gb section enabled by CE2#. R/B#
and R/B2# can be tied together, or they can be used separately to provide independent
indications for each 4Gb section.
On the 16Gb MT29F16G08FAA, R/B# provides a status indication for the 8Gb section
enabled by CE#, and R/B2# does the same for the 8Gb section enabled by CE2#. R/B#
and R/B2# can be tied together, or they can be used separately to provide independent
indications for each 8Gb section.
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# pin. The actual value used for Rp depends on the system timing
requirements. Large values of Rp cause R/B# to be delayed significantly. At the 10 to 90
percent points on the R/B# waveform, rise time is approximately two time constants
(TC).
The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# pin and the total load capacitance.
Refer to Figures 10 and 11 on page 18, which depict approximate Rp values using a
circuit load of 100pF.
Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
t
RC is less than 30ns, use Figure 57 on page 67 for extended data output
TC
=
16
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
R C
×
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RC, use Figure 56 on page 66 for
t
R and transitions HIGH after the
©2006 Micron Technology, Inc. All rights reserved.
Bus Operation