mt29f4g08aaa Micron Semiconductor Products, mt29f4g08aaa Datasheet - Page 22

• Manufacturer Part Number: mt29f4g08aaa
• Description: 4gb, 8gb, And 16gb X8 Nand Flash Memory
• Manufacturer: Micron Semiconductor Products

RANDOM DATA READ 05h-E0h
Figure 13:
PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE START LAST 3Fh
PDF: 09005aef81b80e13/Source: 09005aef81b80eac
4gb_nand_m40a__2.fm - Rev. B 2/07 EN
R/B#
I/Ox
RE#
00h
RANDOM DATA READ Operation
(5 cycles)
Address
30h
The RANDOM DATA READ command enables the user to specify a new column address
so the data at single or multiple addresses can be read. The random read mode is
enabled after a normal PAGE READ (00h-30h) sequence.
Random data can be output after the initial page read by writing an 05h-E0h command
sequence along with the new column address (2 cycles).
The RANDOM DATA READ command can be issued without limit within the page.
Only data on the current page can be read. Pulsing the RE# pin outputs data sequentially
(see Figure 13).
Micron NAND Flash devices have a cache register that can be used to increase the READ
operation speed when accessing sequential pages within a block.
First, issue a normal PAGE READ (00h–30h) command sequence. See Figure 14 on
page 23 for operation details. The R/B# signal goes LOW for
transfer the first page of data from the memory to the data register. After R/B# returns to
HIGH, the PAGE READ CACHE MODE START (31h) command is latched into the
command register. R/B# goes LOW for
the data register to the cache register. After the data register contents are transferred to
the cache register, another PAGE READ is automatically started as part of the 31h
command. Data is transferred from the next sequential page of the memory array to the
data register during the same time data is being read serially (pulsing RE#) from the
cache register. If the total time to output data exceeds
The second and subsequent pages of data are transferred to the cache register by issuing
additional 31h commands. R/B# will stay LOW up to
depending on whether the previous memory-to-data-register transfer was completed
prior to issuing the next 31h command. See Table 18 on page 63 for timing parameters.
If the data transfer from memory to the data register is not completed before the 31h
command is issued, R/B# stays LOW until the transfer is complete.
It is not necessary to output a whole page of data before issuing another 31h command.
R/B# will stay LOW until the previous PAGE READ is complete and the data has been
transferred to the cache register.
To read out the last page of data, the PAGE READ CACHE MODE START LAST (3Fh)
command is issued. This command transfers data from the data register to the cache
register without issuing another PAGE READ (see Figure 14 on page 23).
Crossing block address boundaries when using the PAGE READ CACHE MODE opera-
tion is prohibited.
t R
Data output
22
4Gb, 8Gb, and 16Gb x8 NAND Flash Memory
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DCBSYR1 while data is being transferred from
05h
(2 cycles)
Address
t
DCBSYR2. This time can vary,
t
R, then the PAGE READ is hidden.
E0h
Command Definitions
t
R during the time it takes to
©2006 Micron Technology, Inc. All rights reserved.
Data output