hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 105

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

8
8.1
Figure 72
defining the relevant timing parameters of the device. It
is not intended to either a precise representation of the
typical system environment nor a depiction of the actual
load presented by a production tester. System
designers should use IBIS or other simulation tools to
correlate the timing reference load to a system
environment.
Figure 72
8.2
8.2.1
For DQ and single ended DQS signals output Slew
Rate for falling and rising edges is measured between
V
For differential signals (DQS / DQS) output Slew Rate
is measured between DQS - DQS = –500 mV and
8.2.2
Input Slew Rate for differential signals (CK / CK, DQS /
DQS, RDQS / RDQS) for rising edges are measured
from CK - CK = –250 mV to CK – CK = +500 mV and
Data Sheet
TT
– 250 mV and
represents the timing reference load used in
AC Timing Measurement Conditions
Reference Load for Timing Measurements
Reference Load for Timing Measurements
Slew Rate Measurement Conditions
Output Slew Rate
Input Slew Rate - Differential signals
Manufacturers
V
TT
+ 250 mV.
CK, CK
correlate
Timing Reference Points
DUT
VDDQ
to
DQ
DQS
DQS
RDQS
RDQS
their
106
production
transmission line terminated at the tester electronics.
This reference load is also used for output Slew Rate
characterization. The output timing reference voltage
level for single ended signals is the crosspoint with
The output timing reference voltage level for differential
signals is the crosspoint of the true (e.g. DQS) and the
complement (e.g. DQS) signal.
DQS – DQS = + 500 mV. Output Slew Rate is defined
with the reference load according to
verified by design and characterization, but not subject
to production test.
from CK – CK = +250 mV to CK – CK = –500mV for
falling edges.
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
25 Ohm
test
AC Timing Measurement Conditions
V
TT
conditions,
=
V
DDQ
512-Mbit DDR2 SDRAM
/ 2
09112003-SDM9-IQ3P
generally
Rev. 1.6, 2005-08
Figure 72
a
coaxial
V
and
TT
.