hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 73

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

be issued. During the following DLL re-lock period of
200 clock cycles, ODT must remain off. After the DLL-
Figure 62
3.28
In a given system, Asynchronous Reset event can
occur at any time without prior knowledge. In this
situation, memory controller is forced to drop CKE
asynchronously LOW, immediately interrupting any
valid operation. DRAM requires CKE to be maintained
HIGH for all valid operations as defined in this data
sheet. If CKE asynchronously drops LOW during any
valid operation, the DRAM is not guaranteed to
preserve the contents of the memory array. If this event
Figure 63
Data Sheet
C K , C K
C K E
C M D
C K , C K
C K E
T0
tRP
tAOFD
Input Frequency Change Example during Precharge Power-Down mode
Asynchronous CKE LOW Reset Event
Asynchronous Low Reset Event
T1
N O P
asynchronous reset event
CKE drops low due to an
T2
N O P
changing the frequency
Minimum 2 clocks
required before
T3
N O P
tdelay
T4
N O P
Clocks can be turned off after
Frequency Change
Tx
N O P
occurs here
this point
74
Tx+1
N O P
re-lock period the DRAM is ready to operate with the
new clock frequency.
occurs, the memory controller must satisfy a time delay
(
exist at the input of DRAM before CKE is raised HIGH
again. The DRAM must be fully re-initialized as
described the initialization sequence (Power On and
Initialization, step 4 through 13). DRAM is ready for
normal operation after the initialization sequence. See
Chapter 7 for
t
DELAY
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
before power-down exit
Ty
N O P
Stable new clock
) before turning off the clocks. Stable clocks must
Ty+1
t
N O P
DELAY
stable clocks
tXP
specification.
Ty+2
N O P
512-Mbit DDR2 SDRAM
Ty+3
D LL
R E S E T
Functional Description
09112003-SDM9-IQ3P
200 clocks
ODT is off during
DLL RESET
Rev. 1.6, 2005-08
N O P
Frequ.Ch.
Tz
C om m and
V alid