hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 49

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

3.18
The Read command is initiated by having CS and CAS
LOW while holding RAS and WE HIGH at the rising
edge of the clock. The address inputs determine the
starting column address for the burst. The delay from
the start of the command until the data from the first cell
appears on the outputs is equal to the value of the read
latency (RL). The data strobe output (DQS) is driven
LOW one clock cycle before valid data (DQ) is driven
Figure 24
Figure 25
RL = 5 (AL = 2, CL = 3, BL = 4)
Data Sheet
CK, CK
DQS,
DQS
CMD
DQ
CLK, CLK
DQS,
DQS
DQ
Posted CAS
T0
Read Command
Basic Read Timing Diagram
Read Operation Example 1
READ A
CLK
CLK
AL = 2
T1
NOP
RL = 5
T2
NOP
t
t
RPRE
CH
t
DQS
DQS
DQSQmax
t
DQSCK
CL = 3
T3
NOP
t
CL
t
Dout
QH
t
50
LZ
T4
NOP
onto the data bus. The first bit of the burst is
synchronized with the rising edge of the data strobe
(DQS). Each subsequent data-out appears on the DQ
pin in phase with the DQS signal in a source
synchronous manner. The RL is equal to an additive
latency (AL) plus CAS latency (CL). The CL is defined
by the Mode Register Set (MRS). The AL is defined by
the Extended Mode Register Set (EMRS(1)).
t
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
CK
Dout
t
AC
t
T5
DQSQmax
NOP
Dout A0
Dout
<= t DQSCK
Dout A1
T6
t
RPST
t
NOP
Dout
QH
Dout A2
512-Mbit DDR2 SDRAM
Dout A3
Functional Description
T7
t
09112003-SDM9-IQ3P
HZ
NOP
Rev. 1.6, 2005-08
T8
DO-Read
NOP
BRead523