hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 107

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

8.3.3
Data input setup time (
strobe enabled MR[bit10]=1, is referenced from the
input signal crossing at the
ended data strobe crossing
transition for a rising signal, and from the input signal
crossing at the
strobe crossing
falling signal applied to the device under test.
Data input hold time (
strobe enabled MR[bit10]=1, is referenced from the
Figure 75
Data Sheet
Definition Data Setup (
Data Setup and Hold Time (Single Ended Data Strobes)
V
V
IH/L(dc)
IL(ac)
DQ
level to the single-ended data
at the start of its transition for a
t
DQS
t
DH1
DS1
) with single-ended data
) with single-ended data
V
V
IH(ac)
IH/L(dc)
level to the single-
at the start of its
t
DS
t
DS1
t
DH
) and Hold Time (
108
t
DS
input signal crossing at the
ended data strobe crossing
transition for a rising signal and from the input signal
crossing at the
strobe crossing
falling signal applied to the device under test.
The DQS signal must be monotonic between
and
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
V
IH(dc).MIN
t
DH
t
DH1
.
), Single-Ended Data Strobes
AC Timing Measurement Conditions
V
V
IH/L(ac)
IL(dc)
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF
IL(dc)
IL(ac)
SS
level to the single-ended data
at the end of its transition for a
512-Mbit DDR2 SDRAM
min
min
max
max
V
V
V
V
V
V
V
V
V
IH(dc)
IH/L(ac)
DDQ
IH(ac)
IH(dc)
REF
IL(dc)
IL(ac)
SS
09112003-SDM9-IQ3P
level to the single-
min
min
max
max
Rev. 1.6, 2005-08
at the end of its
V
IL(dc.MAX