hyb18t512160afl-3.7 Infineon Technologies Corporation, hyb18t512160afl-3.7 Datasheet - Page 75

• Manufacturer Part Number: hyb18t512160afl-3.7
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 21
Current State
Power-Down
Self Refresh
Bank(s)
Active
All Banks Idle
Any State other
than
listed above
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
4) CKE must be maintained HIGH while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by
8) “X” means “don’t care (including floating around
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11) t
12)
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations,
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
Table 22
Name (Function)
Write Enable
Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
Data Sheet
See
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
the refresh requirements
HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of
V
Read commands may be issued only after
Precharge or Refresh operations are in progress. See
CKE.MIN
REF
Chapter
must be maintained during Self Refresh operation.
of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid
Clock Enable (CKE) Truth Table for Synchronous Transitions
Data Mask (DM) Truth Table
1)
3.24.2.
CKE
Previous Cycle
(N-1)
L
L
L
L
H
H
H
H
6)
L
L
Current Cycle
(N)
H
L
H
L
L
H
t
XSRD
V
(200 clocks) is satisfied.
REF
6)
)” in Self Refresh and Power Down. However ODT must be driven
t
IS
Chapter 3.25
Command (N)
RAS, CAS, WE
X
DESELECT or NOP Power-Down Exit
X
DESELECT or NOP Self Refresh Exit
DESELECT or NOP Active Power-Down Entry
DESELECT or NOP Precharge Power-Down
AUTOREFRESH
Refer to the Command Truth Table
+ 2×
76
t
CKE
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
+
t
IH
and
.
2) 3)
Chapter 3.24
DM
L
H
Action (N)
Maintain Power-Down
Maintain Self Refresh
Entry
Self Refresh Entry
for a detailed list of restrictions.
512-Mbit DDR2 SDRAM
Valid
X
2)
DQs
09112003-SDM9-IQ3P
Rev. 1.6, 2005-08
Truth tables
1)
1)
Note
t
XSNR
Notes
7)8)11)
7)9)10)11)
8)11)12)
9)12)13)14)
7)9)10)11)15)
9)10)11)15)
7)11)14)16)
17)
period.
4)5)