tc58dvm92a1fti0 TOSHIBA Semiconductor CORPORATION, tc58dvm92a1fti0 Datasheet - Page 23

• Manufacturer Part Number: tc58dvm92a1fti0
• Description: 512-mbit 64m U 8 Bits Cmos Nand E2 Prom
• Manufacturer: TOSHIBA Semiconductor CORPORATION

DEVICE OPERATION
Select page
Select page
RY
RY
CLE
CLE
ALE
ALE
Read Mode (1)
timing details and the block diagram.
/
Read Mode (2)
/
WE
WE
CE
RE
BY
CE
RE
BY
I/O
I/O
N
N
Read mode (1) is set when a “00H” command is issued to the Command register. Refer to Figure 3 below for
00H
01H
M
Figure 3. Read mode (1) operation
Figure 4. Read mode (2) operation
M
M
256
Start-address
Start-address
input
input
M
N
N
527
527
Cell array
Cell array
Busy
Busy
starts on the rising edge of WE in the fourth cycle (after the
address information has been latched). The device will be in
Busy state during this transfer period. The CE signal must stay
Low after the fourth address input and during Busy state.
Serial data can be output synchronously with the RE clock
from the start pointer designated in the address input cycle.
the same as that of Read mode (1). If the start pointer is to be set
after column address 256, use Read mode (2).
from column address 0.
A data transfer operation from the cell array to the register
After the transfer period the device returns to Ready state.
The operation of the device after input of the 01H command is
However, for a Sequential Read, output of the next page starts
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