tc58dvm92a1fti0 TOSHIBA Semiconductor CORPORATION, tc58dvm92a1fti0 Datasheet - Page 30

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tc58dvm92a1fti0

Manufacturer Part Number
tc58dvm92a1fti0
Description
512-mbit 64m U 8 Bits Cmos Nand E2 Prom
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
Multi Block Erase
address have been input.
“71H”.
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
The device carries out a Multi Block Erase operation when it receives a “D0H” command after some sets of the
After the “D0H” command, the total results of Erase operation is shown through the Status Read command
The Status discription of 71H command is following.
RY
/
BY
District 0 Pass/Fail
District 1 Pass/Fail
District 2 Pass/Fail
District 3 Pass/Fail
Total Pass/Fail
Write Protect
Ready/Busy
Not Used
STATUS
D0
Pass: 0
Pass: 0
Pass: 0
Pass: 0
Pass: 0
Do not care
Ready: 1
Protect: 0
Status Read
command
71
OUTPUT
Fail: 1
Fail: 1
Fail: 1
Fail: 1
Fail: 1
Busy: 0
Not Protect: 1
I/O
Fail
Pass
If at least one fail occurred in Max 4 Blocks
erase operation, it shows “Fail” condition.
If fail occurred in District 0 area, it shows
“Fail” condition.
as I/O2.
I/O1 describes total Pass/Fail condition.
I/O2 describes Pass/Fail condition.
I/O3, I/O4 and I/O5 are as same manner
TC58DVM92A1FTI0
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