tc58dvm92a1fti0 TOSHIBA Semiconductor CORPORATION, tc58dvm92a1fti0 Datasheet - Page 32
tc58dvm92a1fti0
Manufacturer Part Number
tc58dvm92a1fti0
Description
512-mbit 64m U 8 Bits Cmos Nand E2 Prom
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TC58DVM92A1FTI0.pdf
(44 pages)
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Reset
Internal erase
Internal V
generated voltage is discharged to 0 volts and the device enters Wait state.
The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally
The response to an “FFH” Reset command input during the various device operations is as follows:
When a Reset (FFH) command is input during programming
When a Reset (FFH) command is input during erasing
voltage
When a Reset (FFH) command is input during Read operation
When a Status Read command (70H) is input after a Reset
When two or more Reset commands are input in succession
RY
RY
RY
RY
RY
RY
/
/
/
/
/
/
BY
BY
BY
BY
BY
BY
PP
80
00
FF
FF
The second
D0
10
70
FF
command is invalid, but the third
(1)
FF
70
t
FF
FF
FF
RST
(max 6 P s)
t
RST
(max 10 P s)
t
RST
(max 500 P s)
FF
(2)
FF
I/O status: Pass/Fail o Pass
I/O status: Ready/Busy o Busy
command is valid.
TC58DVM92A1FTI0
Ready/Busy o Ready
2003-07-11 32/44
00
Figure 10.
Figure 12.
Figure 11.
00
00
Figure 8.
Figure 9.
(3)
FF
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