tc58dvm92a1fti0 TOSHIBA Semiconductor CORPORATION, tc58dvm92a1fti0 Datasheet - Page 31

• Manufacturer Part Number: tc58dvm92a1fti0
• Description: 512-mbit 64m U 8 Bits Cmos Nand E2 Prom
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Internal addressing in relation with the Districts
x The device consists of 4 Districts.
x Each District consists from 1024 erase blocks.
x The allocation rule is follows.
Address input restriction for the Multi Block Erase operation
(Restriction)
Maximum one block should be selected from each District.
(Acceptance)
There is no order limitation of the District for the address input.
Any number of the Districts can be select for the erase operation.
So, for example, following operation are in acceptance.
Example 1 : (60) [District 2] (60) [District 0] (60) [District 1] (D0)
Example 2 : (60) [District 0] (60) [District 1] (60) [District 2] (60) [District 3] (D0)
It requires no mutual address relation between the selected blocks from each District.
To use Multi Block Erase operation, the internal addressing should be conscious in relation with the Districts.
In selecting the blocks for the Multi Block Erase operation, following is the restriction and acceptance.
District 0: Block 0, Block 4, Block 8, Block 12,
District 1: Block 1, Block 5, Block 9, Block 13,
District 2: Block 2, Block 6, Block 10, Block 14,
District 3: Block 3, Block 7, Block 11, Block 15,
···.., Block 4092
···.., Block 4093
···.., Block 4094
···.., Block 4095
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