spl505yc256bst SpectraLinear Inc, spl505yc256bst Datasheet - Page 15

• Manufacturer Part Number: spl505yc256bst
• Description: Clock Generator For Intel Bearlake Chipset
• Manufacturer: SpectraLinear Inc

SPL505YC256BT/
SPL505YC256BS
C P U _S T P #
C P U T
C P U C
Figure 4. CPU_STP# Assertion Waveform
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner, synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
CPU_STP# Deassertion Waveform
1.8mS
CPU_STOP#
PD#
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
Rev 1.4 March 21, 2007
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