cxd3220r Sony Electronics, cxd3220r Datasheet - Page 12

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

6. Asynchronous Communication
6-1. CPU I/F
The CPU I/F controls data communication between the external CPU and the CXD3220R ATF/ARF/CFR
respectively.
Communications between the CPU and CXD3220R include:
The CXD3220R supports 16-bit and 8-bit CPU I/F.
The ATF/ARF/CFR built in the CXD3220R have a 32-bit structure, so all bits can not be accessed with one
access. The target address must be accessed two consecutive times for 16 bits and four consecutive times for
8 bits.
The roles played by the signals communicated between the CXD3220R and the external CPU are given
bellow.
Data [15:0]
ADDRESS [6:0]
XCS
XWR
XRD
XWAIT
XINT
X8/16
1
1) CPU writes data to ATF
2) CPU reads data in ARF
3) CPU writes data to CFR
4) CPU reads data in CFR
5) CXD3220R informs CPU of an interrupt event with an interrupt signal
ATF (Asynchronous Transmit FIFO), ARF (Asynchronous Receive FIFO), CFR (Configuration Register)
In the CXD3220R, the ATF has the capacity of 24 quadlets and the ARF has the capacity of 39 quadlets.
in/out
in
in
in
in
out
out
in
Asynchronous packet receive
Asynchronous packet transmit
internal status, header data read
mode, header data setting
Data for writing to or reading from specified address
Address for writing or reading data
Data destination (CFR or FIFO) and data breakpoint (Write or Confirm) are
discriminated according to the address
Access enable from host bus (low active)
Data write enable signal (low: write)
Data read enable signal (low: read)
Indicates access (read or write) completed to specified address (low active)
Interrupt signal. Indicates some kind of interrupt when low
Type of interrupt and mask specified by CFR
CPU I/F data bus switching
High: 16 bits; low: 8 bits
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CXD3220R
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