cxd3220r Sony Electronics, cxd3220r Datasheet - Page 31

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

(7) Checking for remaining packets still in FIFO
Four quadlets were read in preceding items (1) to (6). They were read continuously because Arf4There was
high.
If Arf4There was low, Async Status must be read after one quadlet is read, to find out if ArfEmpty is high.
Even if Arf4There is high, as in this case, after the fourth quadlet read must be done while checking ArfEmpty
and ArfDc in the same way.
In the above example the Arf4There bit is low, so a maximum of three more quadlets can be predicted, but the
ArfAEmpty bit is high, so there is only one more quadlet in FIFO.
(8) Fifth quadlet of the received packet Read
The CFR ATFWrite/ARFRead register is read.
The data read is "00000001h".
The lower 4 bits of this quadlet are the ackSent field, and this indicates "01h" transmitted as this packet's
Ack_code. This is always written even if the packet is one which does not have Ack_code transmitted, such as
a broadcast packet.
If this value is "04h", the ARF may have become full during receive and quadlets may be missing.
If it is "0Dh", an error was detected in the data field CRC check of the received packet, or data_length and the
actual data length do not match.
ADDRESS
ADDRESS
DATA
DATA
XRD
XCS
XRD
XCS
This indicates that the Dc flag of the ARF is "0", the Dc flag for received data
that was read previously was not up, and that the ARF is almost empty and
ATF is empty.
1Ch
74h
00h
xxx01xxxb
– 31 –
1Dh
75h
00h
xxh
1Eh
76h
00h
xxh
77h
01h
1Fh
xxh
CXD3220R