cxd3220r Sony Electronics, cxd3220r Datasheet - Page 58

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

8. Link-Phy Communication
8-1. Link-Phy Interface Specifications
The CXD3220R and Phy Layer chip communicate using the four signals shown in the block diagram below: D
[0:3], CTL [0:1], LREQ and SCLK.
The roles of the signals are as follows.
The types of communication and their contents are described below.
8-2. Communication
There are four types of communication between Phy Link: request, status, transmit and receive. Except for
request, all commands are initialized by the Phy chip.
8-2-1. Bus controlling
CTL [0:1] controls communication between Phy and the CXD3220R. The communication contents differ
depending on if Phy or the CXD3220R is controlling.
a) Phy controlling
CTL [0:1]
D [0:3]
CTL [0:1]
LREQ
SYSCLK
00
01
10
11
Idle
Status
Receive
Transmit
Name
in/out
in/out
out
in
CXD3220R
Link Layer
Bidirectional data line. D [0:1] and D [0:3] are used for 100Mbps and 200Mbps,
respectively.
Bidirectional control line.
Request signal line from the CXD3220R to Phy chip.
Used for bus access and Phy register Read/Write requests.
System clock (49.12MHz) supplied from Phy to the CXD3220R.
Bus is idle (Default mode).
Phy is sending status information to the CXD3220R.
Phy is sending a packet to the CXD3220R.
Packet transmit authorized for the CXD3220R.
1394
CTL [0:1]
– 58 –
D [0:3]
LREQ
SCLK
Description of Activity
Phy Layer
1394
CXD3220R