cxd3220r Sony Electronics, cxd3220r Datasheet - Page 18

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

6) Diagnostic Register
This register controls or monitors the CXD3220R status.
The register address is 18h and the initial value is 0000_0000h.
Only the EnSp bit and regRW bit are for read/write; other bits are for read/write when the regRW bit is "1" and
for read only when it is "0".
5) Cycle Timer Registers
These registers are composed of the 24.576MHz clock cycle Cycle Offset and the 125µs in its host, and the
Cycle Number that counts one second. The value of all nodes are regulated by the Cycle Master node.
The register address is 14h; it is for read/write, and the initial value is 0000_0000h.
31 to 12
11 to 0
5 to 0
Bit
Bit
Bit
31
30
29
28
27
5
4
3
6
CycleNumber
CycleOffset
ADPSt
ADPCmp
ADPErr
EnSnoop
BsyF
ArbGp
FrGp
regRW
DiffGap
SIGapCnt
Name
Name
Name
The upper 7 bits count seconds (1Hz) and the lower 13 bits count the
Isochronous cycle (8kHz = 125µs). The values are controlled by Control
register Cycle Master and Cycle Timer Enable.
Counts the system clock (24.576MHz). The Cycle Number is incremented
when this counter completes one cycle. The value is controlled by Control
register Cycle Master and Cycle Timer Enable.
The ADP has started.
The ADP has completed.
An error has occurred during ADP processing. In order to clear ADPErr bit,
write "1" to this bit after "1" is written to ADP Control register ADPreset bit.
Receives all packets on the bus regardless of receiver address and format
when "1". Invalid when "0".
Ack to be sent back next is "Ack_BusyB" when "1".
Ack to be sent back next is "Ack_BusyA" when "0".
Bus is in idle state due to Arbitration Reset Gap.
Bus is in idle state due to Fair Gap.
Almost all registers are for read/write when "1".
"1" when there is dispersion in Gap count values in received Self ID. This
value is fixed when the Interrupt register EndSlf bit becomes "1" from "0".
The value is entered when all Gap count values in received Self ID are the
same. "00h" when bus reset is generated.
– 18 –
Function
Function
Function
CXD3220R