cxd3220r Sony Electronics, cxd3220r Datasheet - Page 49

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

CXD3220R
7-4. ADP Structure and Functions
7-4-1. ADP Functions
Retry Function
The ADP is equipped with a function that retransmits a request packet when the Ack code of ack_busy_ has
returned after transmitting that request packet. The CXD3220R supports only single-phase retry. When
resending a packet, the ADP transmits after changing the rt code from 00 to 01 (retry_X). The time interval
during retransmission is defined with the retry_interval set with the Transaction Timeout register. When
retransmission has been retried for the number of times set for the retry_limit with the Transaction Timeout
register, and ack_busy_ is still returned, this is considered to be an error and a busy_timeout is set in the err
code of the ADP Status register followed by generation of ADPErr Interrupt.
Split Timeout Detection Function
The ADP is equipped with a Split Timeout detection function that detects the Timeout until a response packet
returns in the case of a Split Transaction. After a request packet has been transmitted during a Split
Transaction, when the response packet has not returned even after the Split Timeout time defined in the
Transaction Timeout register has elapsed, a busy_timeout is set in the err code of the ADP Status register
followed by the generation of Interrupt.
7-4-2. ADP Structure
Switching Between Transmission and Reception (FIFO Switching)
Switching between transmission and reception (FIFO switching) is controlled with the Direction (d) bit of the
ADP4 register. Two types of FIFO are available to the ADP consisting of a 2KB FIFO and 48 byte FIFO. During
transmission, the 2KB of FIFO becomes the ADPTF (ADP Transmit FIFO), and the 48 bytes of FIFO is not
used. During reception, the 48 byte FIFO becomes the ADPTF, and the 2 KB FIFO becomes the ADPRF (ADP
Receive FIFO). Switching between ADP transmission and reception, including this FIFO switching, is
controlled with the Direction (d) bit of the ADP5 register.
The d bit is read into the ADP when it is started, and the direction of transmission and reception cannot be
changed until the ADP is finished.
Parallel Two-Pair Transmission and Reception FIFO
Other FIFO such as the ARF and ATF are also available to the CXD3220R in parallel with ADP FIFO. This
enables it to perform transmission and reception of normal 1394 packets other than data in parallel with data
exchange performed by the ADP FIFO.
For example, this enables the CXD3220R to accommodate the following:
• Response when a read request has arrived at a CSR or Configuration ROM from another node during data
transfer.
• Response to a Task Management ORB from the initiator during data transfer.
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