cxd3220r Sony Electronics, cxd3220r Datasheet - Page 15

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

2) Node Address Register
These registers are used to monitor root/cycle master status and the total number of nodes connected, and so
on.
The register address is 04h and the initial value is FFFF_0000h.
Only the bus number is for read/write, and the other registers are normally for read only, but the Diagnostic
register can be read/write by setting regRW to "1".
6-2. CFR (Configuration Register)
This is a memory space to store the status information, operation mode and packet header information in the
chip. Read/write with the external CPU can be performed via the CPU I/F.
The address map and register contents are shown below.
Register Description
1) Version/Revision Register
These registers have the CXD3220R version/revision written in them.
The register address is 00h; they are read only, and the default value is 3220_0000h.
31 to 16
31 to 22
21 to 16
15 to 0
11 to 6
5 to 0
Bit
Bit
15
14
13
Version
Revision
Bus Number
Node Number
root
Power Status
CyMas
NodeSum
CFMcontID
Name
Name
Bus number of connected bus
Node number of this link
Root/not root for this link
Cable power status for this mode
Whether or not this link is cycle master
Total number of connected nodes. The value becomes "0" when an error
occurs in the Self ID phase. This value is fixed when the Interrupt register
EndSlf bit becomes "1" from "0".
The Phy-ID value of the contender is loaded.
However, when the CXD3220R node has an ability to become the contender
and this LSI has the Phy-ID value larger than the loaded value, the CXD3220R
itself is the contender. This value is fixed when the Interrupt register EndSlf
bit becomes "1" from "0".
CXD3220R version number
CXD3220R revision number
1: root; 0: not root
1: CPS on; 0: CPS off
1: cycle master; 0: not
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Function
Function
CXD3220R