cxd3220r Sony Electronics, cxd3220r Datasheet - Page 64

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

8-2-5. Receive
When data from the bus is received at Phy, it is sent from Phy to the CXD3220R in the following order.
Phy asserts Receive to the CTL pins and "all 1" to the D pin. Phy indicates the packet header by placing a
Speed code on the D pin. Next it indicates the contents of the packet, and until transmission of the last symbol
in the packet is completed, it holds the CTL pins at Receive. Phy indicates the end of the packet by asserting
Idle to the CTL pins. The Speed code is specified by Phy-Link protocol, and does not include CRC calculation
or other data protect.
Phy can identify if there is data on the bus or not without looking at the packet. This also applies if a packet is
being sent at a faster speed than Phy can receive. In this case, the packet is completed by asserting Idle when
the Data-on state is completed.
If Phy supports a faster transmission speed than the CXD3220R, the CXD3220R detects the Speed code and
ignores the packet until it becomes Idle again.
The timing chart for reception is illustrated below.
Notes)
1. "xx" means that "0" was transmitted, but it is ignored for receive.
2. This LSI supports 100Mbits/s and 200Mbits/s communications.
Speed codes for receive
10000000
0100xxxx
00xxxxxx
D [0:7]
PHY Ctl [0:1]
PHY D [0:3]
Data Rate
100Mbit/s
200Mbit/s
400Mbit/s
(binary)
(hex)
Note) SP means Speed code.
00
00
11
F
10
F
– 64 –
SP
10
D0
10
D1
10
Dn
10
00
00
00
00
CXD3220R