cxd3220r Sony Electronics, cxd3220r Datasheet - Page 43

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

6-5-2-3. Block Receive
The format for Block Receive is shown below.
The first quadlet contains the Destination ID and other packet headers. The second and third quadlets contain
16-bit Source ID and 48-bit Destination Offset for request or the Response code for response. The fourth
quadlet contains Data Length and Extended Transaction code (all "0" except for Lock Transaction). This is
followed by Block data. The last quadlet contains packet receive status.
6-6. Self-ID Packet Receiving Error Processing
In the Self ID phase after bus reset on the CXD3220R, if the Self ID packet could not be received correctly,
Self ID packet receive is stopped immediately and the Node_sum value becomes "0".
The external CPU thus can judge that the Self ID phase could not be completed correctly.
Block Read or Lock Response Receive Format
Block Write or Lock Request Receive Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
destinationID
destinationID
dataLength
dataLength
sourceID
sourceID
destinationOffsetLow
block data
spd
block data
spd
– 43 –
rCode
tLabel
tLabel
destinationOffsetHigh
extendedtCode
extendedtCode
rt
rt
tCode
tCode
acksent
priority
acksent
priority
0
0
CXD3220R