cxd3220r Sony Electronics, cxd3220r Datasheet - Page 28

• Manufacturer Part Number: cxd3220r
• Description: Ieee1394 Link/transaction Layer Controller Lsi For Sbp-2
• Manufacturer: Sony Electronics

6-4. Asynchronous Packet Reception
Basically, if there is room to write the packet in FIFO and the destination_ID matches, then Asynchronous
packets are received. Receive is completed when the packet data is read from the ARF inside the CXD3220R
by the external CPU.
The CXD3220R raises an RxDta flag when a packet is received. (Normally, if the RxDta bit of the CFR Interrupt
Mask register (10h to 13h) is set to "1", XINT goes low when a packet is received and this can be detected.)
Next, the CFR Async Status register (1C to 1Fh) ArfEmpty bit should be low. This indicates that a correct
packet was received.
After this, one quadlet at a time can be read by reading the CFR ATFWrite/ARFRead registers (74h to 77h).
Packet receive is completed by repeating this until the ArfEmpty bit goes high.
However, if the ARF status is empty, read will not be done even if it is executed. In this case, the data read by
the CPU will be the previously read value.
The procedure for receiving a Quadlet Write request packet is given here as an example.
(for 8-bit data interface)
(1) Confirming that the packet was received
The CFR Interrupt register (0Ch) is read to confirm that the 25th bit (RxDta bit) is high.
When only desiring to know information about the register of the lower 2 bits A [1:0] = 00 of the address, only
the address of A [1:0] = 00 may be read. In the case of reading register information for A [1:0] = 01, 10, 11
read the addresses in order starting from the address of A [1:0] = 00.
ADDRESS
DATA
XRD
XCS
This indicates that RxDta only was generated.
0Ch
82h
– 28 –
0Dh
xxh
0Eh
xxh
0Fh
xxh
CXD3220R