ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet

ADSP-TS202S_06

Manufacturer Part Number

ADSP-TS202S_06

Description

TigerSHARC Embedded Processor

Manufacturer

AD [Analog Devices]

Datasheet

1.ADSP-TS202S_06.pdf (48 pages)

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KEY FEATURES

500 MHz, 2.0 ns instruction cycle rate

12M bits of internal—on-chip—DRAM memory

25 mm × 25 mm (576-ball) thermally enhanced ball grid array

Dual-computation blocks—each containing an ALU, a multi-

Dual-integer ALUs, providing data addressing and pointer

Single-precision IEEE 32-bit and extended-precision 40-bit

Integrated I/O includes 14-channel DMA controller, external

TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

package

plier, a shifter, and a register file

manipulation

floating-point data formats and 8-, 16-, 32-, and 64-bit

fixed-point data formats

port, four link ports, SDRAM controller, programmable

flag pins, two timers, and timer expired pin for system

integration

SEQUENCER

FETCH

ADDR

PROGRAM

BTB

IAB

SHIFT

J-BUS ADDR

J-BUS DATA

K-BUS ADDR

K-BUS DATA

I-BUS ADDR

I-BUS DATA

ALU

32-BIT × 32-BIT

MUL

INTEGER

J ALU

DATA ADDRESS GENERATION

32-BIT × 32-BIT

FILE

COMPUTATIONAL BLOCKS

128

32-BIT × 32-BIT

INTEGER

DAB

K ALU

Figure 1. Functional Block Diagram

DAB

128

32-BIT × 32-BIT

12M BITS INTERNAL MEMORY

4 × CROSSBAR CONNECT

FILE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.326.3113

1149.1 IEEE-compliant JTAG test access port for on-chip

On-chip arbitration for glueless multiprocessing

KEY BENEFITS

Provides high performance static superscalar DSP

Performs exceptionally well on DSP algorithm and I/O

Supports low overhead DMA transfers between internal

Eases programming through extremely flexible instruction

Enables scalable multiprocessing systems with low

MEMORY BLOCKS

S-BUS ADDR

S-BUS DATA

(PAGE CACHE)

emulation

operations, optimized for large, demanding multiproces-

sor DSP applications

benchmarks (see benchmarks in

memory, external memory, memory-mapped peripherals,

link ports, host processors, and other (multiprocessor)

DSPs

set and high-level-language-friendly DSP architecture

communications overhead

MUL ALU

128

SHIFT

SOC

I/F

Embedded Processor

SOC BUS

ADSP-TS202S

Table

SDRAM

MULTI-

C-BUS

TigerSHARC

JTAG

PROC

HOST

DMA

CTRL

ARB

OUT

LINK PORTS

JTAG PORT

EXTERNAL

EXT DMA

REQ

PORT

www.analog.com

ADDR

CTRL

DATA

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