ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 24

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS202S
TIMING SPECIFICATIONS
With the exception of DMAR3–0, IRQ3–0, TMR0E, and
FLAG3–0 (input only) pins, all ac timing for the ADSP-TS202S
processor is relative to a reference clock edge. Because input
setup/hold, output valid/hold, and output enable/disable times
are relative to a clock edge, the timing data for the
ADSP-TS202S processor has few calculated (formula-based)
values. For information on ac timing, see
For information on link port transfer timing, see
Voltage, Differential-Signal (LVDS) Electrical Characteristics,
and Timing on Page
General AC Timing
Timing is measured on signals when they cross the 1.25 V level
as described in
onds) are measured between the point that the first signal
reaches 1.25 V and the point that the second signal reaches
1.25 V.
Table 21. AC Asynchronous Signal Specifications
1
2
3
Table 22. Reference Clocks—Core Clock (CCLK) Cycle Time
1
Name
IRQ3–0
DMAR3–0
FLAG3–0
TMR0E
Parameter
t
These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference.
For output specifications on FLAG3–0 pins, see
This pin is a strap option. During reset, an internal resistor pulls the pin low.
CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (t
CCLK
(SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the
1
3
1
2
1
CCLK
Figure 15 on Page
Description
Core Clock Cycle Time
30.
Description
Interrupt Request
DMA Request
FLAG3–0 Input
Timer 0 Expired
29. All delays (in nanosec-
Table
General AC
29.
Figure 9. Reference Clocks—Core Clock (CCLK) Cycle Time
Link Port Low
Rev. C | Page 24 of 48 | December 2006
t
CCLK
Timing.
Pulse Width Low (Min)
2 × t
2 × t
2×t
4×t
The general ac timing data appears in
ac specifications are measured with the load specified in
Figure 36 on Page
strength 4. In order to calculate the output valid and hold times
for different load conditions and/or output drive strengths, refer
to
Fall Time vs. Load Capacitance) and
put Valid vs. Load Capacitance and Drive Strength).
The ac asynchronous timing data for the IRQ3–0, DMAR3–0,
FLAG3–0, and TMR0E pins appears in
SCLK
SCLK
SCLK
SCLK
Figure 37 on Page 38
ns
ns
ns
ns
Ordering Guide on Page
38, and with the output drive strength set to
through
Min
2.0
SCLK
Grade = 050 (500 MHz)
) divided by the system clock ratio
Pulse Width High (Min)
2 × t
2 × t
2×t
Figure 44 on Page 39
SCLK
SCLK
SCLK
46.
Figure 45 on Page 39
Table 22
ns
ns
ns
Table
Max
12.5
21.
and
Table
(Rise and
Unit
ns
29. All
(Out-