ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 20

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS202S
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set
DSP operating modes. During reset, the DSP samples the strap
option pins. Strap pins have an internal pull-up or pull-down
for the default value. If a strap pin is not connected to an over-
driving external pull-up, pull-down, or logic load, the DSP
samples the default value during reset. If strap pins are
Table 16. Pin Definitions—I/O Strap Pins
When default configuration is used, no external resistor is
needed on the strap pins. To apply other configurations, a
500 Ω resistor connected to V
external pull-downs, do not strap these pins directly to V
strap pins require 500 Ω resistor straps.
All strap pins are sampled on the rising edge of RST_IN (deas-
sertion edge). Each pin latches the strapped pin state (state of
the strap pin at the rising edge of RST_IN). Shortly after deas-
sertion of RST_IN, these pins are reconfigured to their normal
functionality.
These strap pins have an internal pull-down resistor, pull-up
resistor, or no-resistor (three-state) on each pin. The resistor
type, which is connected to the I/O pad, depends on whether
RST_IN is active (low) or if RST_IN is deasserted (high).
Table 17
and during normal operation.
Signal
EBOOT
IRQEN
LINK_DWIDTH
SYS_REG_WE
TM1
TM2
TM3
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5 k
pull-up 500
= internal pull-up 40 k
Ω
; pu = internal pull-up 5 k
shows the resistors that are enabled during active reset
Ω
on DSP ID = 0; pd_m = internal pull-down 5 k
Ω
. For more pull-down and pull-up information, see
Type (at
Reset)
I
(pd_0)
I
(pd)
I
(pd)
I
(pd_0)
I (pu)
I (pu)
I (pu)
Ω
DD_IO
; pd_0 = internal pull-down 5 k
is required. If providing
On Pin …
BMS
BM
TMR0E
BUSLOCK
L1BCMPO
L2BCMPO
L3BCMPO
Rev. C | Page 20 of 48 | December 2006
SS
; the
Ω
Description
EPROM Boot
Interrupt Enable
Link Port Input Default Data Width
SYSCON and SDRCON Write Enable
Test Mode 1. Do not overdrive default value during reset.
Test Mode 2. Do not overdrive default value during reset.
Test Mode 3. Do not overdrive default value during reset.
Ω
on DSP bus master; pu_m = internal pull-up 5 k
1 = idle after reset and wait for an external device to boot DSP through the
0 = disable and set IRQ3–0 interrupts to edge-sensitive after reset (default)
1 = enable and set IRQ3–0 interrupts to level-sensitive immediately after reset
0 = 1-bit (default)
1 = 4-bit
0 = one-time writable after reset (default)
1 = always writable
0 = boot from EPROM immediately after reset (default)
on DSP ID = 0; pu_0 = internal pull-up 5 k
external port or a link port
connected to logic inputs, a stronger external pull-up or pull-
down may be required to ensure default value depending on
leakage and/or low level input current of the logic load. To set a
mode other than the default mode, connect the strap pin to a
sufficiently stronger external pull-up or pull-down.
lists and describes each of the DSP’s strap pins.
Table 17. Strap Pin Internal Resistors—Active Reset
(RST_IN = 0) vs. Normal Operation (RST_IN = 1)
Electrical Characteristics on Page
Pin
BMS
BM
TMR0E
BUSLOCK
L1BCMPO
L2BCMPO
L3BCMPO
pd = internal pull-down 5 k
pd_0 = internal pull-down 5 k
pu_0 = internal pull-up 5 k
RST_IN = 0
(pd_0)
(pd)
(pd)
(pd_0)
(pu)
(pu)
(pu)
Ω
Ω
Ω
; pu = internal pull-up 5 k
on DSP ID = 0
Ω
on DSP ID = 0; pu_od_0 = internal
on DSP ID = 0;
22.
Ω
on DSP bus master; pu_ad
RST_IN = 1
(pu_0)
Driven
Driven
(pu_0)
Driven
Driven
Driven
Table 16
Ω
;