ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 12

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS202S
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS202S processor’s input pins are nor-
mally synchronous—tied to a specific clock—a few are
asynchronous. For these asynchronous signals, an on-chip syn-
chronization circuit prevents metastability problems. Use the ac
specification for asynchronous signals when the system design
requires predictable, cycle-by-cycle behavior for these signals.
Table 3. Pin Definitions—Clocks and Reset
Table 4. SCLK Ratio
Signal
SCLKRAT2–0
SCLK
RST_IN
RST_OUT
POR_IN
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground;
pd = internal pull-down 5 k
ID = 0; pu_od_0 = internal pull-up 500
on DSP bus master; pu_ad = internal pull-up 40 k
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
SCLKRAT2–0
000
001
010
011
100
101
110
111
(default)
Ω
to V
DD_IO
, nc = not connected; na = not applicable (always used); V
I (pd)
Type
I
I/A
O
I/A
Ω
; pu = internal pull-up 5 k
Ratio
4
5
6
7
8
10
12
Reserved
Ω
Term
na
na
na
na
na
on DSP ID = 0; pd_m = internal pull-down 5 k
Ω
Rev. C | Page 12 of 48 | December 2006
. For more pull-down and pull-up information, see
Ω
Description
Core Clock Ratio. The DSP’s core clock (CCLK) rate = n × SCLK, where n is user-program-
mable using the SCLKRATx pins to the values shown in
only during reset; connect these pins to V
Table
instruction cycle rate.
System Clock Input. The DSP’s system input clock for cluster bus.The core clock rate
is user-programmable using the SCLKRATx pins.
Domains on Page 9.
Reset. Sets the DSP to a known state and causes program to be in idle state. RST_IN
must be asserted a specified time according to the type of reset operation. For details,
see
Reset Output. Indicates that the DSP reset is complete. Connect to POR_IN.
Power-On Reset for internal DRAM. Connect to RST_OUT.
; pd_0 = internal pull-down 5 k
Reset and Booting on Page
25,
Table
26, and
The output pins can be three-stated during normal operation.
The DSP three-states all outputs during reset, allowing these
pins to get to their internal pull-up or pull-down state. Some
pins have an internal pull-up or pull-down resistor (±30% toler-
ance) that maintains a known value during transitions between
different drivers.
Table 27
DD_IO
= connect directly to V
Ω
9,
Ω
must be satisfied. The core clock rate (CCLK) is the
on DSP ID = 0; pu_0 = internal pull-up 5 k
Table 21 on Page
on DSP bus master; pu_m = internal pull-up 5 k
DD_IO
Ω
or V
to V
Electrical Characteristics on Page
For more information, see Clock
SS
SS
DD_IO
24, and
. All reset specifications in
; epu = external pull-up approx-
Table
; V
SS
4. These pins may change
Figure 14 on Page
= connect directly to V
Ω
on DSP
27.
22.
Ω
SS