ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 6

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS202S
EXTERNAL PORT (OFF-CHIP
MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS202S processor’s external port provides the DSP’s
interface to off-chip memory and peripherals. The 4G word
address space is included in the DSP’s unified address space.
The separate on-chip buses—four 128-bit data buses and four
32-bit address buses—are multiplexed at the SOC interface and
transferred to the external port over the SOC bus to create an
external system bus transaction. The external system bus pro-
vides a single 64-bit data bus and a single 32-bit address bus.
The external port supports data transfer rates of 1G bytes per
second over the external bus.
The external bus can be configured for 32-bit or 64-bit, little-
endian operations. When the system bus is configured for 64-bit
operations, the lower 32 bits of the external data bus connect to
even addresses, and the upper 32 bits connect to odd addresses.
INTERNAL REGISTERS (UREGS)
I NTERNAL MEMORY BLOCK 2
I NTERNAL MEMORY BLOCK 0
INTERNAL MEMORY BLOCK 10
INTERNAL MEMORY BLO CK 6
INTERNAL MEMORY BLO CK 4
INTERNAL MEMORY BLOCK 8
SOC REGISTERS (UREGS)
INTERNAL SPACE
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0x03FFFFFF
0x001F03FF
0x001F0000
0x001E03FF
0x001E0000
0x000CFFFF
0x000C0000
0x0008FFFF
0x0004FFFF
0x0000FFFF
0x0014FFFF
0x00140000
0x0010FFFF
0x00100000
0x00080000
0x00040000
0x00000000
Rev. C | Page 6 of 48 | December 2006
Figure 3. ADSP-TS202S Memory Map
MSSD BANK 2 (MSSD2)
MSSD BANK 3 (MSSD3)
MSSD BANK 1 (MSSD1)
MSSD BANK 0 (MSSD0)
GLOBAL SPACE
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high
order address lines to generate memory bank select signals.
The ADSP-TS202S processor provides programmable memory,
pipeline depth, and idle cycle for synchronous accesses, and
external acknowledge controls to support interfacing to pipe-
lined or slow devices, host processors, and other memory-
mapped peripherals with variable access, hold, and disable time
requirements.
Host Interface
The ADSP-TS202S processor provides an easy and configurable
interface between its external bus and host processors through
the external port. To accommodate a variety of host processors,
the host interface supports pipelined or slow protocols for
INTERNAL MEMORY
PROCESSOR I D 7
PROCESSOR I D 6
PROCESSOR I D 5
PROCESSOR I D 4
PROCESSOR I D 3
PROCESSOR I D 2
PROCESSOR I D 1
PROCESSOR I D 0
HO ST (MSH)
BANK 1 (MS1)
BANK 0 (MS0)
BROADCAST
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0xFFFFFFFF
0x80000000
0x74000000
0x70000000
0x64000000
0x60000000
0x54000000
0x50000000
0x38000000
0x30000000
0x2C000000
0x28000000
0x24000000
0x20000000
0x1C000000
0x18000000
0x14000000
0x10000000
0x0C000000
0x03FFFFFF
0x00000000
0x44000000
0x40000000
O F INTERNAL SPACE
EACH IS A COPY