ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 8

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS202S
• DMA chaining. DMA chaining operations enable applica-
• Two-dimensional transfers. The DMA controller can
external data bus; outputs addresses and memory selects
(MSSD3–0); outputs the IORD, IOWR, IOEN, and
RD/WR strobes; and responds to ACK.
tions to automatically link one DMA transfer sequence to
another for continuous transmission. The sequences can
occur over different DMA channels and have different
transmission attributes.
access and transfer two-dimensional memory arrays on any
DMA transmit or receive channel. These transfers are
implemented with index, count, and modify registers for
both the X and Y dimensions.
REFERENCE
REFERENCE
(OPTIONAL)
DEVICES
DEVICES
CLOCK
(2 MAX)
RESET
LINK
LINK
000
001
Figure 4. ADSP-TS202S Shared Memory Multiprocessing System
LxDATO3–0P/N
LxCLKOUTP/N
LxACKI
LxBCMPO
LxDATI3–0P/N
LxCLKINP/N
LxACKO
LxBCMPI
TMR0E
BM
CONTROLIMP1–0
DS2–0
LINK
Rev. C | Page 8 of 48 | December 2006
CLKS/REFS
SCLK
SCLK_V
V
SCLKRAT2–0
ID2–0
RST_IN
ID2–0
CLKS/REFS
IRQ3–0
FLAG3–0
RST_IN
RST_OUT
POR_IN
REF
JTAG
LINK
ADSP-TS202S #7
ADSP-TS202S #6
ADSP-TS202S #5
ADSP-TS202S #4
ADSP-TS202S #3
ADSP-TS202S #2
ADSP-TS202S #1
ADSP-TS202S #0
REF
CONTROL
ADDR31–0
ADDR31–0
DATA31–0
CONTROL
DATA31–0
BUSLOCK
DMAR3–0
MSSD3–0
BR7–2,0
SDCKE
BR7–1
MS1–0
SDWE
SDA10
IOWR
LDQM
BRST
BOFF
IORD
IOEN
MSH
HBG
RAS
WRL
HBR
CAS
BMS
ACK
DPA
BR1
BR0
CPA
RD
ADDR
DATA
CS
RAS
CAS
DQM
WE
CKE
A10
ADDR
DATA
OE
WE
ACK
CS
CS
ADDR
DATA
ADDR
DATA
PERIPHERALS
(OPTIONAL)
PROCESSOR
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
INTERFACE
MEMORY
GLOBAL
MEMORY
EPROM
SDRAM
AND
BOOT
HOST
CLOCK
CLK