ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 14

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS202S
Table 6. Pin Definitions—External Port Arbitration
1
2
Signal
BR7–0
ID2–0
BM
BOFF
BUSLOCK
HBR
HBG
CPA
DPA
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5 k
pull-up 500
= internal pull-up 40 k
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
imately 5 k
The BRx pin matching the ID2–0 input selection for the processor should be left nc if unused. For example, the processor with ID = 000 has BR0 = nc and BR7–1 = V
This external pull-up resistor may be omitted for the ID = 000 TigerSHARC processor.
Ω
; pu = internal pull-up 5 k
Ω
Ω
to V
on DSP ID = 0; pd_m = internal pull-down 5 k
DD_IO
, nc = not connected; na = not applicable (always used); V
Ω
. For more pull-down and pull-up information, see
Type
I/O
I (pd)
O
I
O/T
(pu_0)
I
I/O/T
(pu_0)
I/O/OD
(pu_od_0)
I/O/OD
(pu_od_0)
Ω
; pd_0 = internal pull-down 5 k
Term
V
na
na
epu
na
epu
epu
epu
epu
DD_IO
2
2
2
1
Rev. C | Page 14 of 48 | December 2006
Description
Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to
arbitrate for bus mastership. Each DSP drives its own BRx line (corresponding to the
value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight
DSPs, set the unused BRx pins high (V
Multiprocessor ID. Indicates the DSP’s ID, from which the DSP determines its order in
a multiprocessor system. These pins also indicate to the DSP which bus request
(BR0–BR7) to assert when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2,
011 = BR3, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7. ID2–0 must have a
constant value during system operation and can change during reset only.
Bus Master. The current bus master DSP asserts BM. For debugging only. At reset this
is a strap pin. For more information, see
Back Off. A deadlock situation can occur when the host and a DSP try to read from
each other’s bus at the same time. When deadlock occurs, the host can assert BOFF
to force the DSP to relinquish the bus before completing its outstanding transaction.
Bus Lock Indication. Provides an indication that the current bus master has locked the
bus. At reset, this is a strap pin. For more information, see
Host Bus Request. A host must assert HBR to request control of the DSP’s external bus.
When HBR is asserted in a multiprocessing system, the bus master relinquishes the
bus and asserts HBG once the outstanding transaction is finished.
Host Bus Grant. Acknowledges HBR and indicates that the host can take control of
the external bus. When relinquishing the bus, the master DSP three-states the
ADDR31–0, DATA63–0, MSH, MSSD3–0, MS1–0, RD, WRL, WRH, BMS, BRST, IORD,
IOWR, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM, and HDQM pins, and the DSP
puts the SDRAM in self-refresh mode. The DSP asserts HBG until the host deasserts
HBR. In multiprocessor systems, the current bus master DSP drives HBG, and all slave
DSPs monitor it.
Core Priority Access. Asserted while the DSP’s core accesses external memory. This
pin enables a slave DSP to interrupt a master DSP’s background DMA transfers and
gain control of the external bus for core-initiated transactions. CPA is an open-drain
output, connected to all DSPs in the system. If not required in the system, leave CPA
unconnected (external pull-ups will be required for DSP ID = 1 through ID = 7).
DMA Priority Access. Asserted while a high priority DSP DMA channel accesses
external memory. This pin enables a high priority DMA channel on a slave DSP to
interrupt transfers of a normal priority DMA channel on a master DSP and gain control
of the external bus for DMA-initiated transactions. DPA is an open-drain output,
connected to all DSPs in the system. If not required in the system, leave DPA uncon-
nected (external pull-ups will be required for DSP ID = 1 through ID = 7).
Ω
Ω
on DSP bus master; pu_m = internal pull-up 5 k
on DSP ID = 0; pu_0 = internal pull-up 5 k
Electrical Characteristics on Page
DD_IO
= connect directly to V
DD_IO
Table 16 on Page
).
Ω
to V
Ω
on DSP ID = 0; pu_od_0 = internal
SS
DD_IO
; epu = external pull-up approx-
22.
Ω
; V
on DSP bus master; pu_ad
20.
Table 16 on Page
SS
= connect directly to V
20.
DD_IO
SS
.