ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 38

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-TS202S
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The time for the voltage on the bus to ramp by ΔV is
dependent on the capacitive load, C
This ramp time can be approximated by the following equation:
The output enable time t
t
t
switches to when the output voltage ramps ΔV from the mea-
sured three-stated output level. t
C
Capacitive Loading
Output valid and hold are based on standard capacitive loads:
30 pF on all pins (see
tions given should be derated by a drive strength related factor
for loads other than the nominal value of 30 pF.
through
itance.
load capacitance. (Note that this graph or derating does not
apply to output disable delays; see
Page
linear outside the ranges shown.
MEASURED_ENA
MEASURED_ENA
L
Figure 37. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 0
, drive current I
37.) The graphs of
Figure 45
Figure 36. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
25
20
15
10
Figure 44
5
0
0
Y = 0.251x + 4.2245
and t
is the interval from when the reference signal
10
OUTPUT
FALL TIME
graphically shows how output valid varies with
PIN
TO
D
RAMP
show how output rise time varies with capac-
20
, and with ΔV equal to 0.4 V.
t
RAMP
Figure
30
as shown in
Figure 37
LOAD CAPACITANCE (pF)
ENA
Y = 0.259x + 3.0842
40
(V
=
is the difference between
36). The delay and hold specifica-
RISE TIME
STRENGTH 0
30pF
DD_IO
(
C
50
RAMP
L
through
= 2.5V)
Output Disable Time on
Δ
L
Figure
50
V
60
, and the drive current, I
is calculated with test load
) I
⁄
70
D
Figure 45
35. The time
1.25V
80
Figure 37
90
Rev. C | Page 38 of 48 | December 2006
DD_IO
may not be
100
= 2.5 V)
D
.
Figure 38. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 1
Figure 39. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 2
Figure 40. Typical Output Rise and Fall Time (10% to 90%, V
vs. Load Capacitance at Strength 3
25
20
15
10
25
20
15
10
25
20
15
10
5
0
5
0
5
0
0
0
0
10
10
10
20
20
20
Y = 0.1527x + 0.7485
30
30
30
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FALL TIME
Y = 0.0949x + 0.8112
Y = 0.0691x + 1.1158
40
40
40
FALL TIME
FALL TIME
(V
(V
(V
STRENGTH 2
STRENGTH 1
STRENGTH 3
DD_IO
DD_IO
DD_IO
50
50
50
Y = 0.1501 x + 0.05
= 2.5V)
= 2.5V)
= 2.5V)
60
60
60
RISE TIME
Y = 0.0861 x + 0.4712
Y = 0.06 x + 1.1362
70
70
70
RISE TIME
RISE TIME
80
80
80
90
90
90
DD_IO
DD_IO
DD_IO
100
100
100
= 2.5 V)
= 2.5 V)
= 2.5 V)