ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 29

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

Table 29. AC Signal Specifications (Continued)
1
2
3
4
5
6
7
8
9
10
11
12
Name
DS2–0
SCLKRAT2–0
ENEDREG
STRAP SYS
JTAG SYS
The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The
For input specifications on FLAG3–0 pins, see
These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.
For additional requirement details, see
RST_IN clock reference is the falling edge of SCLK.
TDO output clock reference is the falling edge of TCK.
Reference clock depends on function.
These pins may change only during reset; recommend connecting it to V
STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, L2BCMPO, and L3BCMPO.
Specifications applicable during reset only.
JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3–0, DMAR3–0, HBR, BOFF, MS1–0, MSH, SDCKE, LDQM, HDQM, BMS, IOWR, IORD, BM, EMU, SDA10,
JTAG system output timing clock reference is the falling edge of TCK.
(All values in this table are in nanoseconds.)
apparent driver overlap, due to output disables being larger than output enables, is not actual.
IOEN, BUSLOCK, TMR0E, DATA63–0, ADDR31–0, RD, WRL, WRH, BRST, MSSD3–0, RAS, CAS, SDWE, HBG, BR7–0, FLAG3–0, L0DATOP3–0, L0DATON3–0,
L1DATOP3–0, L1DATON3–0, L2DATOP3–0, L2DATON3–0, L3DATOP3–0, L3DATON3–0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L2CLKOUTP,
L2CLKOUTN, L3CLKOUTP, L3CLKOUTN, L0ACKI, L1ACKI, L2ACKI, L3ACKI, L0DATIP3–0, L0DATIN3–0, L1DATIP3–0, L1DATIN3–0, L2DATIP3–0,
L2DATIN3–0, L3DATIP3–0, L3DATIN3–0, L0CLKINP, L0CLKINN, L1CLKINP, L1CLKINN, L2CLKINP, L2CLKINN, L3CLKINP, L3CLKINN, L0ACKO, L1ACKO,
L2ACKO, L3ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L2BCMPO, L3BCMPO, L0BCMPI, L1BCMPI, L2BCMPI, L3BCMPI, ID2–0, CTRL_IMPD1–0,
SCLKRAT2–0, DS2–0, ENEDREG.
8
11, 12
9, 10
8
REFERENCE
CLOCK
OUTPUT
SIGNAL
SIGNAL
THREE-
STATE
INPUT
Description
Static Pins—Must Be Constant
Static Pins—Must Be Constant
Static Pins—Must Be Connected to V
Strap Pins
JTAG System Pins
Reset and Booting on Page
Table
21.
OUTPUT
VALID
1.25V
DISABLE
OUTPUT
Rev. C | Page 29 of 48 | December 2006
Figure 15. General AC Parameters Timing
9.
1.25V
DD_IO
t
SCLK
/V
SS
OR
SS
.
1.25V
t
TCK
—
—
—
1.5
+2.5
SETUP
INPUT
—
—
—
0.5
+10.0
OUTPUT
OUTPUT
ENABLE
INPUT
HOLD
HOLD
—
—
—
—
+12.0
—
—
—
—
–1.0
—
—
—
—
—
—
—
—
—
—
ADSP-TS202S
—
—
—
SCLK
TCK