M58WR064 STMICROELECTRONICS [STMicroelectronics], M58WR064 Datasheet - Page 20

• Manufacturer Part Number: M58WR064
• Description: 64 Mbit 4Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58WR064ET, M58WR064EB
2. Each subsequent Word to be verified is latched
3. Finally, after all Words have been verified, write
If the Verify Phase is successfully completed the
memory remains in Read Status Register mode. If
the Program/Erase Controller fails to reprogram a
given location, the error will be signaled in the Sta-
tus Register.
Exit Phase. Status Register P/E.C. bit SR7 set to
‘1’ indicates that the device has returned to Read
mode. A full Status Register check should be done
to ensure that the block has been successfully pro-
grammed. See the section on the Status Register
for more details.
Quadruple Enhanced Factory Program
Command
The Quadruple Enhanced Factory Program com-
mand can be used to program one or more pages
of four adjacent Words in parallel. The four Words
must differ only for the addresses A0 and A1.
Dual operations are not supported during Quadru-
ple Enhanced Factory Program operations and
the command cannot be suspended.
The Quadruple Enhanced Factory Program com-
mand has four phases: the Setup Phase, the Load
Phase where the data is loaded into the buffer, the
combined Program and Verify Phase where the
loaded data is programmed to the memory and
then automatically checked and reprogrammed if
necessary and the Exit Phase. Unlike the En-
hanced Factory Program it is not necessary to re-
submit the data for the Verify Phase. The Load
Phase and the Program and Verify Phase can be
repeated to program any number of pages within
the block.
Setup Phase. The Quadruple Enhanced Factory
Program command requires one Bus Write opera-
tion to initiate the load phase. After the setup
command is issued, read operations output the
Status Register data. The Read Status Register
command must not be issued as it will be
interpreted as data to program.
Load Phase. The Load Phase requires 4 cycles
to load the data (refer to Table 7, Factory Program
Commands and Figure 30, Quadruple Enhanced
Factory Program Flowchart). Once the first Word
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with a new Bus Write operation. The Words
must be written in the same order as in the
Program Phase. The address can remain the
Start Address or be incremented. If any address
that is not in the same block as the Start
Address is given with data FFFFh, the Verify
Phase terminates. Status Register bit SR0
should be read to check that the P/E.C. is ready
for the next Word.
one Bus Write operation with data FFFFh to any
address outside the block containing the Start
Address, to terminate the Verify Phase.
of each Page is written it is impossible to exit the
Load phase until all four Words have been written.
Two successive steps are required to issue and
execute the Load Phase of the Quadruple En-
hanced Factory Program command.
1. Use one Bus Write operation to latch the Start
2. Each subsequent Word to be programmed is
The memory is now set to enter the Program and
Verify Phase.
Program and Verify Phase. In the Program and
Verify Phase the four Words that were loaded in
the Load Phase are programmed in the memory
array and then verified by the Program/Erase Con-
troller. If any errors are found the Program/Erase
Controller reprograms the location. During this
phase the Status Register shows that the Pro-
gram/Erase Controller is busy, Status Register bit
SR7 set to ‘0’, and that the device is not waiting for
new data, Status Register bit SR0 set to ‘1’. When
Status Register bit SR0 is set to ‘0’ the Program
and Verify phase has terminated.
Once the Verify Phase has successfully complet-
ed subsequent pages in the same block can be
loaded and programmed. The device returns to
the beginning of the Load Phase by issuing one
Bus Write operation to latch the Address and the
first of the four new Words to be programmed.
Exit Phase. Finally, after all the pages have been
programmed, write one Bus Write operation with
data FFFFh to any address outside the block con-
taining the Start Address, to terminate the Load
and Program and Verify Phases.
Status Register bit SR7 set to ‘1’ and bit SR0 set
to ‘0’ indicate that the Quadruple Enhanced Facto-
ry Program command has terminated. A full Status
Register check should be done to ensure that the
block has been sucessfully programmed. See the
section on the Status Register for more details.
If the Program and Verify Phase has successfully
completed the memory returns to Read mode. If
Address and the first Word of the first Page to
be programmed. For subsequent Pages the first
Word address can remain the Start Address (in
which case the next Page is programmed) or
can be any address in the same block. If any
address with data FFFFh is given that is not in
the same block as the Start Address, the device
enters the Exit Phase. For the first Load Phase
Status Register bit SR7 should be read after the
first Word has been issued to check that the
command has been accepted (bit SR7 set to
‘0’). This check is not required for subsequent
Load Phases.
latched with a new Bus Write operation. The
address is only checked for the first Word of
each Page as the order of the Words to be
programmed is fixed.