M58WR064 STMICROELECTRONICS [STMicroelectronics], M58WR064 Datasheet - Page 62

• Manufacturer Part Number: M58WR064
• Description: 64 Mbit 4Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58WR064ET, M58WR064EB
Table 38. Bank and Erase Block Region 1 Information
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(P+1A)h =53h
(P+1B)h =54h
(P+1C)h =55h
(P+1D)h =56h
(P+1E)h =57h
(P+1F)h =58h
(P+21)h =5Ah
(P+22)h =5Bh
(P+23)h =5Ch
(P+24)h =5Dh
(P+25)h =5Eh
(P+26)h =5Fh
(P+19)h =52h
(P+20)h =59h
M58WR064ET (top)
Offset
Data
0Fh
00h
11h
00h
00h
01h
07h
00h
00h
01h
64h
00h
01h
03h
(P+1C)h =55h
(P+1D)h =56h
(P+23)h =5Ch
(P+24)h =5Dh
(P+2C)h =65h
(P+2D)h =66h
(P+1A)h =53h
(P+1B)h =54h
(P+1E)h =57h
(P+1F)h =58h
(P+21)h =5Ah
(P+22)h =5Bh
(P+25)h =5Eh
(P+26)h =5Fh
(P+2A)h =63h
(P+2B)h =64h
M58WR064EB (bottom)
(P+19)h =52h
(P+20)h =59h
(P+27)h =60h
(P+28)h =61h
(P+29)h =62h
Offset
Data
01h
00h
11h
00h
00h
02h
07h
00h
20h
00h
64h
00h
01h
03h
06h
00h
00h
01h
64h
00h
01h
Number of identical banks within Bank Region 1
Number of program or erase operations allowed in region 1:
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in other banks
while a bank in same region is programming
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in other banks
while a bank in this region is erasing
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Types of erase block regions in region 1
n = number of erase block regions with contiguous same-size
erase blocks.
Symmetrically blocked banks have one blocking region.
Bank Region 1 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 1 (Erase Block Type 1)
Minimum block erase cycles × 1000
Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved 5Eh 01 5Eh 01
Bank Region 1 (Erase Block Type 1): Page mode and
synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
Bank Region 1 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 1 (Erase Block Type 2)
Minimum block erase cycles × 1000
Bank Regions 1 (Erase Block Type 2): BIts per cell, internal
ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
Description
(2)