M58WR064 STMICROELECTRONICS [STMicroelectronics], M58WR064 Datasheet - Page 64

• Manufacturer Part Number: M58WR064
• Description: 64 Mbit 4Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58WR064ET, M58WR064EB
Note: 1. The variable P is a pointer which is defined at CFI offset 15h.
64/82
(P+34)h =6Dh
(P+35)h =6Eh
(P+36)h =6Fh
(P+3A)h =73h
(P+3B)h =74h
(P+3C)h =75h
(P+3D)h =76h
(P+3E)h =77h
(P+37)h =70h
(P+38)h =71h
(P+39)h =72h
M58WR064ET (top)
Offset
2. Bank Regions. There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 con-
tains the banks that are made up of the parameter and main blocks.
Data
03h
07h
00h
20h
00h
64h
00h
01h
03h
(P+3C)h =75h
(P+3D)h =76h
(P+3E)h =77h
M58WR064EB (bottom)
Offset
Data
03h
Bank Region 2 (Erase Block Type 1): Page mode and
synchronous
mode capabilities (defined in table 10)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
Bank Region 2 Erase Block Type 2 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Minimum block erase cycles × 1000
Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
Bank Region 2 (Erase Block Type 2): Page mode and
synchronous
mode capabilities (defined in table 10)
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
Feature Space definitions
Reserved
Bank Region 2 (Erase Block Type 2)
Description