M58WR064 STMICROELECTRONICS [STMicroelectronics], M58WR064 Datasheet - Page 63

• Manufacturer Part Number: M58WR064
• Description: 64 Mbit 4Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Note: 1. The variable P is a pointer which is defined at CFI offset 15h.
Table 39. Bank and Erase Block Region 2 Information
(P+2A)h =63h
(P+2B)h =64h
(P+2C)h =65h
(P+2D)h =66h
(P+2E)h =67h
(P+2F)h =68h
(P+31)h =6Ah
(P+32)h =6Bh
(P+33)h =6Ch
(P+27)h =60h
(P+28)h =61h
(P+29)h =62h
(P+30)h =69h
M58WR064ET (top)
M58WR064ET (top)
Offset
Offset
2. Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks
that are made up of the parameter and main blocks.
Data
Data
01h
00h
11h
00h
00h
02h
06h
00h
00h
01h
64h
00h
01h
(P+33)h =6Ch
(P+34)h =6Dh
(P+2E)h =67h
(P+2F)h =68h
(P+31)h =6Ah
(P+32)h =6Bh
(P+35)h =6Eh
(P+36)h =6Fh
(P+3A)h =73h
(P+3B)h =74h
M58WR064EB (bottom)
M58WR064EB (bottom)
(P+30)h =69h
(P+37)h =70h
(P+38)h =71h
(P+39)h =72h
Offset
Offset
Data
Data
03h
0Fh
00h
11h
00h
00h
01h
07h
00h
00h
64h
00h
01h
01h
Bank Region 1 (Erase Block Type 2): Page mode and
synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3-7: reserved
Number of identical banks within bank region 2
Number of program or erase operations allowed in bank region
2:
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in other banks
while a bank in this region is programming
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Number of program or erase operations allowed in other banks
while a bank in this region is erasing
Bits 0-3: Number of simultaneous program operations
Bits 4-7: Number of simultaneous erase operations
Types of erase block regions in region 2
n = number of erase block regions with contiguous same-size
erase blocks.
Symmetrically blocked banks have one blocking region.
Bank Region 2 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase blocks
Bits 16-31: n×256 = number of bytes in erase block region
Bank Region 2 (Erase Block Type 1)
Minimum block erase cycles × 1000
Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
BIts 5-7: reserved
M58WR064ET, M58WR064EB
Description
Description
(2)
63/82